[SOLVED] J-Link Base and DA14531 device

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  • [SOLVED] J-Link Base and DA14531 device

    Hi,

    I've done multiple designs with the DA14531 using a different debugger / programmer (DA14531 EVK). However, this time I need 1.8V capability and my existing debugger won't do that. So I got a segger J-Link Base debugger / programmer and the 6-pin adapter for tag connect: segger.com/products/debug-prob…ers/6-pin-needle-adapter/

    My main problem is being able to detect the device (from Keil MDK). See attached error message. See attached relevant schematic for my board.

    Nothing else is connected to RST (I have disconnected CHG-STOP connection to another part of the circuit - it was not the problem). I have also ohm'd out the connections between the j-link base debugger 20-pin header and the DA14531 MOD pins SWDIO, SWCLK, RST, and VTREF. So, there is no wiring mistake, pin connections are correct.
    There is nothing else connected to SWDIO.
    There is a level translator input (A) connected to SWDCLK (see schematic), but I can't see how that would make a difference. I can try and disconnect it if you think it would be useful.
    I have scoped the signals SWDIO, SWDCLK and RST while DA14531 is connected. I see some valid-looking data at SWDIO, but nothing at SWDCLK other than constant 0.36V (same as RST, nothing but 0.36V). To me it looks like j-link base assumes RST is active low, but DA14531 is active high (and pulled down internally with 25kOhm). This is why the orange light is lit.
    When I disconnect DA14531 and scope the signals SWDIO, SWDCLK and RST at the J-link 20pin header, the signal RST will go low and just before that there is some valid looking data on SWDIO and clocks on SWDCLK. I feel like the issue has to do with RST (active high vs active low).

    One time I did get a connection using segger commander and it looked like this:

    Source Code

    1. DLL version V6.40, compiled Oct 26 2018 15:06:02
    2. Connecting to J-Link via USB...O.K.
    3. Firmware: J-Link V11 compiled Sep 22 2022 14:53:28
    4. Hardware version: V11.00
    5. S/N: 51025885
    6. License(s): GDB
    7. VTref=1.806V
    8. Type "connect" to establish a target connection, '?' for help
    9. J-Link>connect
    10. Please specify device / core. <Default>: CORTEX-M0
    11. Type '?' for selection dialog
    12. Device>connect CORTEX-M0
    13. Please specify target interface:
    14. J) JTAG (Default)
    15. S) SWD
    16. F) FINE
    17. I) ICSP
    18. C) C2
    19. T) cJTAG
    20. TIF>S
    21. Specify target interface speed [kHz]. <Default>: 4000 kHz
    22. Speed>
    23. Device "CORTEX-M0+" selected.
    24. Connecting to target via SWD
    25. Found SW-DP with ID 0x0BC11477
    26. Scanning AP map to find all available APs
    27. AP[1]: Stopped AP scan as end of AP map has been reached
    28. AP[0]: AHB-AP (IDR: 0x04770031)
    29. Iterating through AP map to find AHB-AP to use
    30. AP[0]: Core found
    31. AP[0]: AHB-AP ROM base: 0xE00FF000
    32. CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
    33. Found Cortex-M0 r0p1, Little endian.
    34. FPUnit: 4 code (BP) slots and 0 literal slots
    35. CoreSight components:
    36. ROMTbl[0] @ E00FF000
    37. ROMTbl[0][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
    38. ROMTbl[0][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
    39. ROMTbl[0][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
    40. Cortex-M0 identified.
    Display All


    But I can't seem to get a connection anymore through commander, and certainly have never got connection through keil. Any ideas what could be the issue here? I've been stuck for days

    Thank you!

    Erik
    Images
    • schematic.png

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    • error.png

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  • Hi,
    As mentioned in the support request you opened in our support ticket system:

    The interface of J-Link and the 6-Pin needle adapter specifies pad no 3 as nRESET, so the J-Link is behaving correctly:
    segger.com/products/debug-prob…eedle-adapter/#schematics

    It expects an active low nRESET (#RESET / not RESET), which is in accordance with the specification.
    Thus, as the DA14531 has a RESET pin instead of nRESET pin,
    the board design would have to make sure that the signal is negated to apply to debug header/interface specification.

    Even though we would recommend to adjust the board design accordingly,
    you could also make sure that the nRESET pin is not connected, which should work as long as you do not require
    to reset the device via reset pin.

    BR
    Fabian
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

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