Hello,
I can not debug the NXP example project "hello world" for the IMXRT1050-EVK in the external SDRAM (IAR EWARM 9.10.1 in configuration "sdram_txt_debug") with a JLINK Plus probe. Debugging with the integrated DAP works as expected.
The attached EWARM debug log ewarmDebugLog.txt (using JLink V7.52d, also tested with V7.70c) shows several "Core did not halt after reset" entries and "Failed to read SP and PC from vector table at 0x8000'0000" but it also shows that the download&verification have been successful. After downloading I can stop execution (PC is somewhere in internal RAM but not correct) and see in the disassembly view that the correct data has been written to the SDRAM.
Changing the reset strategy does not help.
If I change the location of the interrupt table in the used ICF file "MIMXRT1052xxxx_sdram_txt.icf" to the internal RAM (ITCM) debugging works as expected:
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
I still get some "Core did not halt" messages but finally the execution stops at main in SDRAM.
In the attached debug log it looks like EWARM/Jlink is trying to read the stack pointer and PC from the interrupt table in external SDRAM before initializing the external SDRAM.
Does somebody know how it is possible to place all code in SDRAM and still debug using JLINK?
Kind regards,
Stefan
I can not debug the NXP example project "hello world" for the IMXRT1050-EVK in the external SDRAM (IAR EWARM 9.10.1 in configuration "sdram_txt_debug") with a JLINK Plus probe. Debugging with the integrated DAP works as expected.
The attached EWARM debug log ewarmDebugLog.txt (using JLink V7.52d, also tested with V7.70c) shows several "Core did not halt after reset" entries and "Failed to read SP and PC from vector table at 0x8000'0000" but it also shows that the download&verification have been successful. After downloading I can stop execution (PC is somewhere in internal RAM but not correct) and see in the disassembly view that the correct data has been written to the SDRAM.
Changing the reset strategy does not help.
If I change the location of the interrupt table in the used ICF file "MIMXRT1052xxxx_sdram_txt.icf" to the internal RAM (ITCM) debugging works as expected:
define symbol m_interrupts_start = 0x00000000;
define symbol m_interrupts_end = 0x000003FF;
I still get some "Core did not halt" messages but finally the execution stops at main in SDRAM.
In the attached debug log it looks like EWARM/Jlink is trying to read the stack pointer and PC from the interrupt table in external SDRAM before initializing the external SDRAM.
Does somebody know how it is possible to place all code in SDRAM and still debug using JLINK?
Kind regards,
Stefan