[SOLVED]Trying to flash custom board with i.MXRT1176 - "Failed to prepare RAMCode using RAM" and "Error while determining flash info"

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  • [SOLVED]Trying to flash custom board with i.MXRT1176 - "Failed to prepare RAMCode using RAM" and "Error while determining flash info"

    We are developing a custom board with an i.MXRT1176 processor, that is using different flash than the one used on the NXP MIMXRT1170-EVK eval board. Building code that only uses the internal RAM and uploading it to the RT1176 does work just fine. With that we've confirmed the design of the hardware, we were also able to talk to the primary flash via our firmware. So we are sure that the flash is attached correctly. But building a software that utilises the flash and trying to flash it to our device does fail (compare log below).
    The flash on our board does have different timings to the one used on the eval board, we saw that using the timings of the IS25WP128-JBLE of the eval board does lead to failing communication with out flash. We need to initialise the RT1176 quite a bit differently than the eval board does it in order to speak to our ext flash. The external flash on our custom board is a QSPI flash and connected to FlexSPI1, just like the IS25WP128-JBLE on the eval board. Now to my actual questions:

    • Do I understand the SEGGER wiki correctly, that by specifying -device MIMXRT1176xxxA_M7 the JLink expects a IS25WP128-JBLE to be present and initialises the RT1176 before writing to flash accordingly?
    • Thus in order to flash to the flash on our custom board, we need to write a custom J-Link script?
      • Is HandleBeforeFlashProg() the correct function to use for initialising the FlexSPI of the RT1176 for communication with our external flash? I expect that we need to tell the JLink how to initialise the FlexSPI interface of the RT1176 in order to talk to our external flash.
      • Do we need to touch other functions, e.g. HandleBeforeMemAccessWrite() or HandleAfterMemAccessWrite()?
    • Can you give me some more details to the error messages posted by the JLinkGDBServer?
      • What does the JLink tries to do when it reports "ERROR: Failed to prepare RAMCode using RAM"?
      • What is the flash info it tries to determine ("Error while determining flash info (Bank @ 0x30000000)")? The Address 0x30000000 lines up with the region that the RT1176 memory mappes to the FlexSPI1, which is the interface that our flash is connected to.


    Source Code

    1. $ JLinkGDBServer -endian little -noir -speed 4000 -port 2331 -device MIMXRT1176xxxA_M7 -if SWD -halt -reportuseraction -powertarget 1
    2. SEGGER J-Link GDB Server V7.70e Command Line Version
    4. JLinkARM.dll V7.70e (DLL compiled Aug 31 2022 17:11:20)
    6. Command line: -endian little -noir -speed 4000 -port 2331 -device MIMXRT1176xxxA_M7 -if SWD -halt -reportuseraction -powertarget 1
    7. -----GDB Server start settings-----
    8. GDBInit file: none
    9. GDB Server Listening port: 2331
    10. SWO raw output listening port: 2332
    11. Terminal I/O port: 2333
    12. Accept remote connection: yes
    13. Generate logfile: off
    14. Verify download: off
    15. Init regs on start: off
    16. Silent mode: off
    17. Single run mode: off
    18. Target connection timeout: 0 ms
    19. ------J-Link related settings------
    20. J-Link Host interface: USB
    21. J-Link script: none
    22. J-Link settings file: none
    23. ------Target related settings------
    24. Target device: MIMXRT1176xxxA_M7
    25. Target device parameters: none
    26. Target interface: SWD
    27. Target interface speed: 4000kHz
    28. Target endian: little
    30. Connecting to J-Link...
    31. J-Link is connected.
    32. Device "MIMXRT1176XXXA_M7" selected.
    33. Firmware: J-Link V11 compiled Aug 30 2022 11:47:49
    34. Hardware: V11.00
    35. S/N: 51023305
    36. Feature(s): GDB
    37. Checking target voltage...
    38. Target voltage: 3.30 V
    39. Listening on TCP/IP port 2331
    40. Connecting to target...
    41. Found SW-DP with ID 0x6BA02477
    42. DPIDR: 0x6BA02477
    43. CoreSight SoC-400 or earlier
    44. Scanning AP map to find all available APs
    45. AP[3]: Stopped AP scan as end of AP map has been reached
    46. AP[0]: AHB-AP (IDR: 0x84770001)
    47. AP[1]: AHB-AP (IDR: 0x24770011)
    48. AP[2]: APB-AP (IDR: 0x54770002)
    49. Iterating through AP map to find AHB-AP to use
    50. AP[0]: Core found
    51. AP[0]: AHB-AP ROM base: 0xE00FD000
    52. CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
    53. Found Cortex-M7 r1p2, Little endian.
    54. FPUnit: 8 code (BP) slots and 0 literal slots
    55. CoreSight components:
    56. ROMTbl[0] @ E00FD000
    57. [0][0]: E00FE000 CID B105100D PID 000BB4C8 ROM Table
    58. ROMTbl[1] @ E00FE000
    59. [1][0]: E00FF000 CID B105100D PID 000BB4C7 ROM Table
    60. ROMTbl[2] @ E00FF000
    61. [2][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
    62. [2][1]: E0001000 CID B105E00D PID 000BB002 DWT
    63. [2][2]: E0002000 CID B105E00D PID 000BB00E FPB-M7
    64. [2][3]: E0000000 CID B105E00D PID 000BB001 ITM
    65. [1][1]: E0041000 CID B105900D PID 001BB975 ETM-M7
    66. [1][2]: E0042000 CID B105900D PID 004BB906 CTI
    67. [0][1]: E0043000 CID B105900D PID 001BB908 CSTF
    68. Cache: Separate I- and D-cache.
    70. I-Cache L1: 32 KB, 512 Sets, 32 Bytes/Line, 2-Way
    71. D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    72. Connected to target
    73. Waiting for GDB connection...Connected to 127.0.0.1
    74. Reading all registers
    75. Read 4 bytes @ address 0x00223104 (Data = 0xF7DEE7FE)
    76. Read 2 bytes @ address 0x00223104 (Data = 0xE7FE)
    77. Received monitor command: reset 2
    78. Reset: Halt core after reset via DEMCR.VC_CORERESET.
    79. Reset: Reset device via reset pin
    80. Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
    81. Reset: Reconnecting and manually halting CPU.
    82. Found SW-DP with ID 0x6BA02477
    83. DPIDR: 0x6BA02477
    84. CoreSight SoC-400 or earlier
    85. AP map detection skipped. Manually configured AP map found.
    86. AP[0]: AHB-AP (IDR: Not set)
    87. AP[0]: Core found
    88. AP[0]: AHB-AP ROM base: 0xE00FD000
    89. CPUID register: 0x411FC272. Implementer code: 0x41 (ARM)
    90. Found Cortex-M7 r1p2, Little endian.
    91. Reset: Halt core after reset via DEMCR.VC_CORERESET.
    92. Reset: Reset device via AIRCR.VECTRESET.
    93. AfterResetTarget() start
    94. Valid application detected. Setting PC / SP manually.
    95. PC = 0x0080A615
    96. SP = 0x01140210
    97. Clean & invalidate cached CPU registers
    98. AfterResetTarget() end
    99. Resets core & peripherals using RESET pin.
    100. Downloading 512 bytes @ address 0x30000400
    101. Downloading 52 bytes @ address 0x30001000
    102. Downloading 1024 bytes @ address 0x30002000
    103. Downloading 15792 bytes @ address 0x30002400
    104. Downloading 16000 bytes @ address 0x300061B0
    105. Downloading 16048 bytes @ address 0x3000A030
    106. Downloading 16032 bytes @ address 0x3000DEE0
    107. Downloading 16032 bytes @ address 0x30011D80
    108. Downloading 16048 bytes @ address 0x30015C20
    109. Downloading 16176 bytes @ address 0x30019AD0
    110. Downloading 16224 bytes @ address 0x3001DA00
    111. Downloading 16288 bytes @ address 0x30021960
    112. Downloading 9032 bytes @ address 0x30025900
    113. Downloading 8 bytes @ address 0x30027C48
    114. Downloading 4 bytes @ address 0x30027C50
    115. Downloading 4 bytes @ address 0x30027C54
    116. Downloading 964 bytes @ address 0x30027C58
    117. ERROR: Failed to prepare RAMCode using RAM
    118. Error while determining flash info (Bank @ 0x30000000)
    119. Writing register (PC = 0x300024b4)
    120. GDB closed TCP/IP connection (Socket 10)
    121. ^CRestoring target state and closing J-Link connection...
    122. Shutting down...
    Display All

  • Hi,

    We will close this thread, as you also contacted us via the Support Ticket system.
    Please make sure to keep communication to one channel for future request.
    Otherwise
    • information might be lost between channels
    • this might lead to a higher work load on our side, resulting in slower response time
    Best regards,
    Sebastian
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
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