[SOLVED] SES for ARM 6.32 having 'cannot honor width suffix' assembler errors

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  • [SOLVED] SES for ARM 6.32 having 'cannot honor width suffix' assembler errors

    Hello-

    I have the following code in a project for the STM32L062 Cortex M0 processor:

    Source Code

    1. .syntax unified
    2. .global OSp_StartKernel
    3. .extern OS_TaskRUNNING
    4. .extern OS_TaskNEW
    5. .section .text
    6. .align 0
    7. .thumb_func
    8. OSp_StartKernel:
    9. ldr r0, =OS_TaskRUNNING
    10. ldr r2, [r0]
    11. ldr sp, [r2]
    12. pop {r4-r11}
    13. pop {r0-r3}
    14. pop {r12}
    15. pop {lr}
    16. pop {lr}
    17. pop {r1}
    18. cpsie i
    19. bx lr
    Display All

    This is code that compiled fine under earlier versions of SES with other Cortex M0 chips from both TI and ST. Now, I am getting "cannot honor width suffix" errors as shown in the image. Internet searches seem to indicate that this is related to using thumb instructions, but also that the 'syntax unified' directive should take care of this. I didn't find any 'allow thumb' options for the assembler in the project options, so what setting do I need to alter to get this to compile?
    Images
    • assembler_error.jpg

      30.47 kB, 403×120, viewed 50 times
  • Hello,

    Thank you for your inquiry.
    Thumb is not the issue here, it is not like you could use something else on Cortex-M :D

    What most likely happened that the update of the toolchain brought some stricter rules on how assembly code may be aligned and where the older assembler might have marked such files just with a warning or ignored it. The new version apparently is more strict (which is usually good as it points out flaws in old code bases which sometimes only worked accidentally).

    Either way, we recommend to specifically align all of your thumb_funcs.
    Could you try .balign 2 instead if .align 0 ?
    Does that work for you?

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
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  • Hello-

    Switching to '.balign 2' results in the same errors. I would have been surprised if that did work as I would have expected alignment on 0 to be more restrictive and therefore less likely to have issues.

    EDIT: Also having errors with balign 4 and 8...

    The post was edited 1 time, last by Eqqman ().

  • Hello,

    Unfortunately the issue is not reproducible for us.
    Could you attach an example project that shows the describe behaviour?

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hello,

    Are you sure that the same code worked on another Cortex-M0+?
    Because the Syntax you are using is not supported for Cortex-M0+ which is Arm architecture Arm v6M. So this could have never have worked with a Arm V6M target.

    This code will only work on Arm v7M and later, such as Cortex-M4 or M7.

    For more information we recommend to check out the Arm v6M architecture manual.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hello- thank you for the time spent looking into this. I went back to double-check what was used, the code is sourced from "Embedded Systems: Real-Time Operating Systems for Arm Cortex M Microcontrollers", Jonathan Valvano, ISBN: 9781466468863, which from the title can be seen to cover Cortex M in general and not M0 specifically. Both the processors I used from TI and ST were from the Cortex M4 line, so while I am working with M0 now I was mistaken that I had been using M0 originally. I will have to rewrite the code to be Thumb-only, this case can be marked as closed.
  • Hello,

    OK thank you for clarifying.

    Regarding RTOS, maybe our RTOS embOS would be of interest for you.
    It runs on any MCU and is a perfect fit to Embedded Studio:
    segger.com/products/rtos/embos/

    It also comes with hundreds of BSP example projects for all kinds of boards and architectures that work out of the box.
    So you can get started with your application directly without having to worry how to start an RTOS.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.