[SOLVED] CPU_HW_HALT() Function Pointer Null.

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  • [SOLVED] CPU_HW_HALT() Function Pointer Null.

    Hello! I am currently configuring support for debugging an Cortex-A53 core through Ozone.
    Here is some quick info about my enviornment.
    I am using the JLink Plus Compact. Firmware is V10. Hardware is V10.10
    Ozone 3.26h

    The issue I am running into currently is that Ozone doesn't halt the CPU so the debugger can attach. When I attempt to run my configuration. A Popup window pops up that says this.
    ---------------------------
    J-Link V7.66f Error
    ---------------------------
    CPU_HW_Halt(): Function pointer is NULL
    ---------------------------

    If anyone has run into this before or knows how to set the CPU_HW_HALT() function. I would greatly appreciate any feedback. I believe if I can configure halting the debugger will be able to connect.

    Here is a look at the output when I run my jlinkscript.

    Source Code

    1. Device "CORTEX-A53" selected.
    2. ConfigTargetSettings() start
    3. XXXXXXXXXX Configuring settings
    4. X SetEtmBaseAddr was successful
    5. X SetCoreBaseAddr was successful
    6. XXXXXXXXXX Val, 0x00000000
    7. ConfigTargetSettings() end
    8. InitTarget() start
    9. XXXXXXXXXX Setup Target
    10. Memory access: CPU temp. halted: https://wiki.segger.com/Memory_accesses#Legacy_stop_mode
    11. InitTarget() end
    12. Connect failed. Resetting via Reset pin and trying again.
    13. ConfigTargetSettings() start
    14. XXXXXXXXXX Configuring settings
    15. X SetEtmBaseAddr was successful
    16. X SetCoreBaseAddr was successful
    17. XXXXXXXXXX Val, 0x00000000
    18. ConfigTargetSettings() end
    19. InitTarget() start
    20. XXXXXXXXXX Setup Target
    21. HDE Lock: 0xFFFFFFFF
    22. A53_DBG_0 Lock: 0xFFFFFFFF
    23. InitTarget() end
    24. TotalIRLen = 16, IRPrint = 0x000411
    25. JTAG chain detection found 2 devices:
    26. #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
    27. #1 Id: 0x14711093, IRLen: 12, Unknown device
    28. DPv0 detected
    29. AP map detection skipped. Manually configured AP map found.
    30. AP[0]: AXI-AP (IDR: Not set)
    31. AP[1]: APB-AP (IDR: Not set)
    32. AP[2]: JTAG-AP (IDR: Not set)
    33. Using preconfigured AP[1] as APB-AP
    34. AP[1]: APB-AP found
    35. DebugRegs + CTI manually specified. ROM table scan skipped.
    36. Cortex-A53 @ 0x80410000 (configured)
    37. CoreCTI @ 0x80420000 (configured)
    38. Debug architecture: ARMv8
    39. 6 code breakpoints, 4 data breakpoints
    40. Processor features:
    41. EL0 support: AArch64 + AArch32
    42. EL1 support: AArch64 + AArch32
    43. EL2 support: AArch64 + AArch32
    44. EL3 support: AArch64 + AArch32
    45. FPU support: Single + Double + Conversion
    46. ARMv8-A/R: The connected J-Link (S/N 850100973) uses an old firmware module V0 with known problems / limitations.
    47. Add. info (CPU temp. halted)
    48. CPU could not be halted
    49. Failed to temporarily halt CPU
    50. Specific core setup failed.
    Display All

    Here is a look at my jlinkscript

    C Source Code: a53_0 jlinkscript

    1. // Run variables
    2. __constant U32 _USE_CORRECT_DBG_ADDR = 1;
    3. __constant U32 _USE_JTAG_SETUP = 0;
    5. // Target Variables
    6. __constant U32 _ADDR_DBG = 0x80410000;
    7. __constant U32 _ADDR_DBG_ROM = 0x80400000;
    8. __constant U32 _INDEX_AP = 1;
    9. __constant U32 _EDEC_OFFSET = 0x24; // External Debug Execution Control Register
    10. __constant U32 _LAR_OFFSET = 0xFB0;
    11. __constant U32 _LSR_OFFSET = 0xFB4;
    12. __constant U32 _CONTROL_OFFSET = 0x88; // CORESIGHT_SOC_TSGEN
    13. __constant U32 _CNTCR = 0x00FE900000; // Halt the counter based on state of primary input. Halt on Debug
    14. __constant U32 _CNTCR_HDBG_ON = 0x100;
    15. __constant U32 _EDESR = 0x00FEC10020; // External Debug Event Status Register
    16. __constant U32 _EDESR_HALT = 0x100;
    18. // DAP variables
    19. __constant U32 _DP_CTRL_STAT_BIT_DBGPWRUPREQ = (1 << 30);
    20. __constant U32 _DP_CTRL_STAT_BIT_SYSPWRUPREQ = (1 << 28);
    21. __constant U32 _DP_CTRL_STAT_BIT_STICKYERR = (1 << 5);
    23. int ConfigTargetSettings( void ){
    24. JLINK_SYS_Report("XXXXXXXXXX Configuring settings");
    25. JLINK_ExecCommand("EnableRemarks");
    27. if(JLINK_ExecCommand("CORESIGHT_SetETMBaseAddr = 0x80440000 ForceUnlock = 1 APIndex = 1") == 0)
    28. {
    29. JLINK_SYS_Report("X SetEtmBaseAddr was successful");
    30. }
    32. JLINK_CORESIGHT_AddAP(0, CORESIGHT_CUSTOM_AP);
    33. JLINK_CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
    34. JLINK_CORESIGHT_AddAP(2, CORESIGHT_JTAG_AP);
    35. CPU = CORTEX_A53;
    36. JLINK_CORESIGHT_IndexAPBAPToUse = _INDEX_AP;
    37. CORESIGHT_CoreBaseAddr = _ADDR_DBG;
    38. JLINK_ExecCommand("CORESIGHT_SetCSCTICoreBaseAddr=0x80420000");
    40. JLINK_SYS_Report1("XXXXXXXXXX Val, ", CORESIGHT_CoreBaseAddr);
    41. return 0;
    42. }
    44. int InitTarget(void)
    45. {
    46. JTAG_Reset();
    47. JTAG_DRPre = 0;
    48. JTAG_DRPost = 1;
    49. JTAG_IRPre = 0;
    50. JTAG_IRPost = 12;
    51. JTAG_IRLen = 4;
    52. JTAG_AllowTAPReset = 1;
    53. return 0;
    54. }
    56. int SetupTarget( void ){
    57. U32 A53_DBG_0;
    58. U32 LOCK_STATUS;
    59. U32 HDE_INSERT;
    60. U32 HALT_INSERT;
    61. JLINK_ExecCommand("EnableRemarks");
    63. JLINK_SYS_Report("XXXXXXXXXX Setup Target");
    65. A53_DBG_0 = 0x00FEC10000;
    67. // Unlock the Lock access register
    68. JLINK_MEM_WriteU32(A53_DBG_0 + _LAR_OFFSET, 0xC5ACCE55);
    70. // Write acces into External Debug Status and Control Register
    71. HDE_INSERT = JLINK_MEM_ReadU32(A53_DBG_0 + _CONTROL_OFFSET);
    72. HDE_INSERT = HDE_INSERT | (1 << 14);
    73. JLINK_MEM_WriteU32(A53_DBG_0 + _CONTROL_OFFSET, HDE_INSERT);
    74. JLINK_SYS_Report1("HDE Lock: ", HDE_INSERT);
    76. // Read value
    77. LOCK_STATUS = JLINK_MEM_ReadU32(A53_DBG_0 + _LSR_OFFSET);
    78. JLINK_SYS_Report1("A53_DBG_0 Lock: ", LOCK_STATUS);
    80. //Manually HALT?
    81. JLINK_MEM_WriteU32(_EDESR, _EDESR_HALT);
    83. return 0;
    84. }
    Display All

    The post was edited 1 time, last by jordanmuehl0001 ().

  • Hi,

    Hard to say what is going wrong without knowing your target device.

    SetupTarget() definitely looks wrong.
    The JLINK_MEM_Write() calls write memory *through* the core which actually halts the core before the write-call. So it is nonesense to halt the core via another MEM_Write() call to the EDESR.
    Just delete the SetupTarget() for now. All you do in there is generic debug setup and done by J-Link anyhow.

    The error message sounds like an internal error that should not happen.
    With the Cortex-A53 based devices we have tested so far, we have never encountered this and right now I do not see how this can happen.
    If you can provide a J-Link log file, this might give some insight:
    wiki.segger.com/Enable_J-Link_log_file
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Alex. Thanks for the response :)

    I have removed the setup target function. Here is a logfile that was produced when running it again. One thing that might be useful to note. The output above where it can identify the El1-3 and debug architecture only appears when the core is halted before hand and our board is not running properly. When we have restarted the machine and everything is running well we get this output where we are having issues with the CPU-TAP. One thing this might be from is that we are using a Xilinx board with a J-Tag chain which has changed in their documentation. We are using a Zynq Ultrascale+ .
    Note: They specify above in their TRM that the JTag-chain length is always 16 bits but this diagram has it at 18 bits in length.Here is the previous version of the document

    And updated

    Here is the Log file
    JLinkGDBServer.log

    You mentioned that MEM_Write() writes through the core. Is this a situation where I should be mapping the APB-AP and and writing through there.




    Thank you for the help. If there is anymore info you need please let me know

    - Jordan

  • It has been some time when I have had the UltraScale+ on my desk.
    Getting access to the Cortex-R5 on it was no fun...Never worked on the Cortex-A cores of that chip. (That time ago we did not even have support for the Cortex-A53)

    jordanmuehl0001 wrote:

    Note: They specify above in their TRM that the JTag-chain length is always 16 bits but this diagram has it at 18 bits in length
    That's easy: The diagram is garbage.
    The ARM DAP is IR = 4 bits wide, so [3:0] and not [5:0], making the chain: 6 + 6 + 4 = 16

    Also, setting up the JTAG chain is not sufficient because the ARM DAP must be explicitly enabled (UltraScale+ specific)
    An excerpt from the script to enable access to the Cortex-R5 below.
    If you open a ticket (referencing this thread) using a company e-mail address and assure that you are not going to share the script with any 3rd party, we can provide the script for the UltraScale+ Cortex-R5 core to you, which you then can adapt for the Cortex-A53.


    BR
    Alex


    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.