Hello,

I have an STM32G474RC which utilizes dual banking. Bank1 is located at, 0x0800 0000 and bank 2 is located at 0x0804 0000. Does J-Flash V7.60c have the capability to flash Bank2 and then Bank1 in that order? As I understand it, with Dual Banking and RDP1, if Bank1 is flashed first then processor will boot from this location after Bank1 is flashed. Then when the J-Link attempts to finish the sequence and flash bank2 it will run into the RDP1 setting which took place while flashing bank1 and we will not have the capability to flash the second bank.

Or does J-Flash automatically handling this issue before the MCU has a chance to boot? I don't see any specific option for the bank flashing sequence.

Thank you for you time,

Hello Fabian,

We are having issues that may or may not be related to this flashing process. As a part of the debug we are validating the flashing sequence. Since the MCU is being flashed with RDP1 we can't verify that both banks are flashed so we have to verify the process that J-Flash is following is expected.

When using J-Flash, is there a way we can validate the reset & halt is the default first step? I see on wiki.segger.com/UM08003_JFlash…-Flash_for_the_first_time under Actions performed by "Production Programming" "F7" that the process is as follows"

1. Init steps
   
2. erase sectors
   
3. program
   
4. verify
   
5. start app
   
6. secure chip
   
7. exit steps
   

Is the "Halt" command part of the Init step and then the a final "Go" command, which starts the CPU part of the exit step? Where can I find these default configs in J-Flash?

Apologies, I don't have a lot of experience with J-Flash so this programming software is relatively new to me.

Thank you,