[ABANDONED] Cannot halt CPU

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  • [ABANDONED] Cannot halt CPU

    Dear community,
    I'm trying to debug my Amlogic A113X SoC using JLink v10.1 adapter via JTAG. This is quad Cortex-A53 SoC. This is what I get in JLinkExe under Linux:

    Source Code

    1. SEGGER J-Link Commander V7.62a (Compiled Feb 23 2022 17:02:50)
    2. DLL version V7.62a, compiled Feb 23 2022 17:02:35
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Link V10 compiled Nov 2 2021 12:14:50
    6. Hardware version: V10.10
    7. S/N: 50125191
    8. License(s): GDB
    9. VTref=3.300V (fixed)
    12. Type "connect" to establish a target connection, '?' for help
    13. J-Link>connect
    14. Please specify device / core. <Default>: CORTEX-A53
    15. Type '?' for selection dialog
    16. Device>
    17. Please specify target interface:
    18. J) JTAG (Default)
    19. S) SWD
    20. T) cJTAG
    21. TIF>
    22. Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    23. JTAGConf>
    24. Specify target interface speed [kHz]. <Default>: 4000 kHz
    25. Speed>
    26. Device "CORTEX-A53" selected.
    29. Connecting to target via JTAG
    30. TotalIRLen = 4, IRPrint = 0x01
    31. JTAG chain detection found 1 devices:
    32. #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
    33. DPv0 detected
    34. Scanning AP map to find all available APs
    35. AP[1]: Stopped AP scan as end of AP map has been reached
    36. AP[0]: APB-AP (IDR: 0x44770002)
    37. Iterating through AP map to find APB-AP to use
    38. AP[0]: APB-AP found
    39. Scanning ROMTbl @ 0x80000000
    40. [0]Comp[0] @ 0x00000000: ROM Table
    41. Scanning ROMTbl @ 0x00000000
    42. [1]Comp[0] @ 0x00001000: CSTF
    43. [1]Comp[1] @ 0x00002000: TPIU
    44. [1]Comp[2] @ 0x00003000: ETB
    45. [1]Comp[3] @ 0x00004000: ATBR
    46. [1]Comp[4] @ 0x00005000: CTI
    47. [1]Comp[5] @ 0x00006000: TSG
    48. [1]Comp[6] @ 0x00400000: ROM Table
    49. Scanning ROMTbl @ 0x00400000
    50. [2]Comp[0] @ 0x00410000: Cortex-A53
    51. [2]Comp[1] @ 0x00420000: CSS600-CTI
    52. Core found. Stopped ROM table scan: https://wiki.segger.com/ROMTableScan
    53. Cortex-A53 @ 0x00410000 (detected)
    54. CoreCTI @ 0x00420000 (detected)
    55. Debug architecture: ARMv8
    56. 6 code breakpoints, 4 data breakpoints
    57. Processor features:
    58. EL0 support: AArch64 + AArch32
    59. EL1 support: AArch64 + AArch32
    60. EL2 support: AArch64 + AArch32
    61. EL3 support: AArch64 + AArch32
    62. FPU support: Single + Double + Conversion
    63. Add. info (CPU temp. halted)
    64. CPU could not be halted
    65. Failed to temporarily halt CPU
    66. TotalIRLen = 4, IRPrint = 0x01
    67. JTAG chain detection found 1 devices:
    68. #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
    69. DPv0 detected
    70. Scanning AP map to find all available APs
    71. AP[1]: Stopped AP scan as end of AP map has been reached
    72. AP[0]: APB-AP (IDR: 0x44770002)
    73. Iterating through AP map to find APB-AP to use
    74. AP[0]: APB-AP found
    75. Scanning ROMTbl @ 0x80000000
    76. [0]Comp[0] @ 0x00000000: ROM Table
    77. Scanning ROMTbl @ 0x00000000
    78. [1]Comp[0] @ 0x00001000: CSTF
    79. [1]Comp[1] @ 0x00002000: TPIU
    80. [1]Comp[2] @ 0x00003000: ETB
    81. [1]Comp[3] @ 0x00004000: ATBR
    82. [1]Comp[4] @ 0x00005000: CTI
    83. [1]Comp[5] @ 0x00006000: TSG
    84. [1]Comp[6] @ 0x00400000: ROM Table
    85. Scanning ROMTbl @ 0x00400000
    86. [2]Comp[0] @ 0x00410000: Cortex-A53
    87. [2]Comp[1] @ 0x00420000: CSS600-CTI
    88. Core found. Stopped ROM table scan: https://wiki.segger.com/ROMTableScan
    89. Cortex-A53 @ 0x00410000 (detected)
    90. CoreCTI @ 0x00420000 (detected)
    91. Debug architecture: ARMv8
    92. 6 code breakpoints, 4 data breakpoints
    93. Processor features:
    94. EL0 support: AArch64 + AArch32
    95. EL1 support: AArch64 + AArch32
    96. EL2 support: AArch64 + AArch32
    97. EL3 support: AArch64 + AArch32
    98. FPU support: Single + Double + Conversion
    99. Add. info (CPU temp. halted)
    100. CPU could not be halted
    101. Failed to temporarily halt CPU
    103. ****** Error: Specific core setup failed.
    105. Cannot connect to target.
    106. J-Link>
    Display All

    It says "Specific core setup failed". I had another output some time ago (did not change anything in my debug setup):

    Source Code

    1. SEGGER J-Link Commander V7.62a (Compiled Feb 23 2022 17:02:50)
    2. DLL version V7.62a, compiled Feb 23 2022 17:02:35
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Link V10 compiled Nov 2 2021 12:14:50
    6. Hardware version: V10.10
    7. S/N: 50125191
    8. License(s): GDB
    9. VTref=3.300V (fixed)
    12. Type "connect" to establish a target connection, '?' for help
    13. J-Link>connect
    14. Please specify device / core. <Default>: CORTEX-A53
    15. Type '?' for selection dialog
    16. Device>
    17. Please specify target interface:
    18. J) JTAG (Default)
    19. S) SWD
    20. T) cJTAG
    21. TIF>
    22. Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    23. JTAGConf>
    24. Specify target interface speed [kHz]. <Default>: 4000 kHz
    25. Speed>
    26. Device "CORTEX-A53" selected.
    29. Connecting to target via JTAG
    30. TotalIRLen = 4, IRPrint = 0x01
    31. JTAG chain detection found 1 devices:
    32. #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
    33. DPv0 detected
    34. Scanning AP map to find all available APs
    35. AP[1]: Stopped AP scan as end of AP map has been reached
    36. AP[0]: APB-AP (IDR: 0x44770002)
    37. Iterating through AP map to find APB-AP to use
    38. AP[0]: APB-AP found
    39. Scanning ROMTbl @ 0x80000000
    40. [0]Comp[0] @ 0x00000000: ROM Table
    41. Scanning ROMTbl @ 0x00000000
    42. [1]Comp[0] @ 0x00001000: CSTF
    43. [1]Comp[1] @ 0x00002000: TPIU
    44. [1]Comp[2] @ 0x00003000: ETB
    45. [1]Comp[3] @ 0x00004000: ATBR
    46. [1]Comp[4] @ 0x00005000: CTI
    47. [1]Comp[5] @ 0x00006000: TSG
    48. [1]Comp[6] @ 0x00400000: ROM Table
    49. Scanning ROMTbl @ 0x00400000
    50. [2]Comp[0] @ 0x00410000: Cortex-A53
    51. [2]Comp[1] @ 0x00420000: CSS600-CTI
    52. Core found. Stopped ROM table scan: https://wiki.segger.com/ROMTableScan
    53. Cortex-A53 @ 0x00410000 (detected)
    54. CoreCTI @ 0x00420000 (detected)
    55. Debug architecture: ARMv8
    56. 6 code breakpoints, 4 data breakpoints
    57. Add. info (CPU temp. halted)
    58. CPU could not be halted
    59. Failed to temporarily halt CPU
    60. TotalIRLen = 4, IRPrint = 0x01
    61. JTAG chain detection found 1 devices:
    62. #0 Id: 0x5BA00477, IRLen: 04, CoreSight JTAG-DP
    63. DPv0 detected
    64. Scanning AP map to find all available APs
    65. AP[1]: Stopped AP scan as end of AP map has been reached
    66. AP[0]: APB-AP (IDR: 0x44770002)
    67. Iterating through AP map to find APB-AP to use
    68. AP[0]: APB-AP found
    69. Scanning ROMTbl @ 0x80000000
    70. [0]Comp[0] @ 0x00000000: ROM Table
    71. Scanning ROMTbl @ 0x00000000
    72. [1]Comp[0] @ 0x00001000: CSTF
    73. [1]Comp[1] @ 0x00002000: TPIU
    74. [1]Comp[2] @ 0x00003000: ETB
    75. [1]Comp[3] @ 0x00004000: ATBR
    76. [1]Comp[4] @ 0x00005000: CTI
    77. [1]Comp[5] @ 0x00006000: TSG
    78. [1]Comp[6] @ 0x00400000: ROM Table
    79. Scanning ROMTbl @ 0x00400000
    80. [2]Comp[0] @ 0x00410000: Cortex-A53
    81. [2]Comp[1] @ 0x00420000: CSS600-CTI
    82. Core found. Stopped ROM table scan: https://wiki.segger.com/ROMTableScan
    83. Cortex-A53 @ 0x00410000 (detected)
    84. CoreCTI @ 0x00420000 (detected)
    85. Debug architecture: ARMv8
    86. 6 code breakpoints, 4 data breakpoints
    87. Add. info (CPU temp. halted)
    88. CPU could not be halted
    89. Failed to temporarily halt CPU
    91. ****** Error: EDSCR[HDE]: Cannot enable halting debug mode
    92. Specific core setup failed.
    94. Cannot connect to target.
    Display All


    Now it says "EDSCR[HDE]: Cannot enable halting debug mode" and missing CPU features list.
    Looks like it can read registers but cannot execute commands, like "halt" command.
    I have prepared device to JTAG debug using SoC vendor instructions. I cannot understand what's going on - is it incomplete vendor's instructions, faulty connection or what? Please help me figure this out.
    JLink adapter firmware is up to date.