[SOLVED] Instruction Trace window only displays "No Data"

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  • [SOLVED] Instruction Trace window only displays "No Data"

    I am trying to get Trace information recorded with an Ozone project running on a GigaDevice GD32F303ZK MCU using a J-Trace Pro Cortex-M (S/N: 752001773). However when I try to look at the instruction Trace window data, all it shows is "No Data".

    I have successfully performed the "Ozone — Trace Tutorial" from Segger's website using that J-Trace unit and the Segger Cortex-M Trace Reference Board V1.2, so the J-Trace and Ozone installation check out OK. Also, general debugging (stepping, breakpoints, looking at data, etc) all works fine with either JTAG or SWD configured.

    So I'm wondering if there's an initialization step I haven't set up or configured correctly. I'd like to eliminate that possibility before I go to the EE about a possible problem on the board (this is the first time we have tried to get trace data from this project).


    The reference manual for the somewhat similar STM32F103ZE chip says this about the trace pins:

    By default, these pins are NOT assigned. They can be assigned by setting the TRACE_IOEN and TRACE_MODE bits in the MCU Debug component configuration register. This configuration has to be done by the debugger host.

    (I don't see anything similar mentioned in the GD32F303ZK reference, but I think the GD32 behavior for the trace pin initialization is likely to be the same as the STM32).

    The only thing I see in the Trace Reference board's project about initializing trace is a line in the .jdebug project file, "Project.SetTraceSource ("Trace Pins");", and I have that same line in the project file for my GD32 board.

    Is there some initialization I'm neglecting that will enable the Trace Data?

    This is what is displayed in the Ozone Console window:

    Source Code

    1. Debug.Start();
    2. Device "GD32F303ZK" selected.
    3. TotalIRLen = 9, IRPrint = 0x0011
    4. JTAG chain detection found 2 devices:
    5. #0 Id: 0x4BA00477, IRLen: 04, CoreSight JTAG-DP
    6. #1 Id: 0x790007A3, IRLen: 05, Unknown device
    7. DPv0 detected
    8. Scanning AP map to find all available APs
    9. AP[1]: Stopped AP scan as end of AP map has been reached
    10. AP[0]: AHB-AP (IDR: 0x24770011)
    11. Iterating through AP map to find AHB-AP to use
    12. AP[0]: Core found
    13. AP[0]: AHB-AP ROM base: 0xE00FF000
    14. CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
    15. Found Cortex-M4 r0p1, Little endian.
    16. FPUnit: 6 code (BP) slots and 2 literal slots
    17. CoreSight components:
    18. ROMTbl[0] @ E00FF000
    19. [0][0]: E000E000 CID B105E00D PID 000BB00C SCS-M7
    20. [0][1]: E0001000 CID B105E00D PID 003BB002 DWT
    21. [0][2]: E0002000 CID B105E00D PID 002BB003 FPB
    22. [0][3]: E0000000 CID B105E00D PID 003BB001 ITM
    23. [0][4]: E0040000 CID B105900D PID 000BB9A1 TPIU
    24. [0][5]: E0041000 CID 00000000 PID 00000000 ???
    25. Connected to target device.
    26. Reset: Halt core after reset via DEMCR.VC_CORERESET.
    27. Reset: Reset device via AIRCR.SYSRESETREQ.
    28. Elf.GetBaseAddr(); // returns 0x8041800
    29. Target.ReadU32 (0x08041800); // returns 0x4, data is 0x20000530
    30. Target.SetReg ("SP", 0x20000530);
    31. Elf.GetEntryPointPC(); // returns 0x80774B4
    32. Target.SetReg ("PC", 0x80774B4);
    33. J-Link: Flash download: Bank 0 @ 0x08000000: Skipped. Contents already match
    34. Elf.GetBaseAddr(); // returns 0x8041800
    35. Target.ReadU32 (0x08041800); // returns 0x4, data is 0x20000530
    36. Target.SetReg ("SP", 0x20000530);
    37. Elf.GetEntryPointPC(); // returns 0x80774B4
    38. Target.SetReg ("PC", 0x80774B4);
    39. Executed J-Link command "SelectTraceSource=1"
    40. Startup complete (PC=0x08076DEA)
    41. Debug.Continue();
    Display All

    Thanks for any suggestions.

  • Hello,

    Thank you for your inquiry.
    The behaviour is expected. The GD32F3 series does not have an ETM so the chip does not provide trace support.
    Quote from GigaDevice when we ran into a similar issue with the GD32F4 series:
    " Only the GD32F10x (HD, XD, CL lines) and GD32F20x include ETM function."

    Other Arm trace types are also not available.
    You could take a look at software tracing maybe:
    wiki.segger.com/General_inform…rent_software_trace_types

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • SEGGER - Nino wrote:

    The GD32F3 series does not have an ETM so the chip does not provide trace support

    Well I'll be damned. That's disappointing to say the least. The board started out with an STM32F103 design, then briefly moved to a GD32F103ZK design, then to the GD32F303ZK. I never noticed the ETM disappearing from the datasheet.

    Thanks for quickly setting me straight.

    The GD32F303xx datasheet does mention the Cortex-M4 on it does support these things:
    • Instrument Trace Macrocell (ITM)
    • Trace Port Interface Unit (TPIU)
    Do either of them provide anything like even a minimal trace capability that the J-Trace can use to some advantage? (I'm asking before I've even started researching what those things are, but I'd appreciate any pointers that might save me from wasting my time in a rabbit hole).

  • Hello,

    Technically SWO trace would be possible via ITM/TPIU (see linked Wiki article). However the datasheet does not mention any SWO pins.
    I recommend to contact Gigadevice Support as we have no additional information if SWO is available or not.

    If not, the only thing remaining is software tracing.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.