Hello,
at the time being Segger JLink always selects hart #0 when it comes to RISC-V debugging.
I'm trying to debug SiFive U54-MC processor that has 5 hearts and this is a very unfortunate limitation from Segger.
I tried selecting the hart manually, after the link is established, by programming the needed hartsel in the dmcontrol register using the JLink scripting language, but it looks like with every operation that the debugger does (like stepping, reading/writing memory, refreshing registers, etc.) JLink sets the hartsel to 0 again. Therefore it's not possible to debug the needed core even if I selected it manually
Is there a way to disable this somehow or there is a way to provide the hart ID for JLink to use?
If no, are there any plans on adding this feature someday?
Sincerely,
Maxim.
at the time being Segger JLink always selects hart #0 when it comes to RISC-V debugging.
I'm trying to debug SiFive U54-MC processor that has 5 hearts and this is a very unfortunate limitation from Segger.
I tried selecting the hart manually, after the link is established, by programming the needed hartsel in the dmcontrol register using the JLink scripting language, but it looks like with every operation that the debugger does (like stepping, reading/writing memory, refreshing registers, etc.) JLink sets the hartsel to 0 again. Therefore it's not possible to debug the needed core even if I selected it manually
Is there a way to disable this somehow or there is a way to provide the hart ID for JLink to use?
If no, are there any plans on adding this feature someday?
Sincerely,
Maxim.