[ABANDONED] JLINLK Can config cortex-m55 CSW register HPROT filed [28bit] by CORESIGHT_AHBAPSWDefaultSettings?

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  • [ABANDONED] JLINLK Can config cortex-m55 CSW register HPROT filed [28bit] by CORESIGHT_AHBAPSWDefaultSettings?


    hello everyone,
    I want to config cortex-m55 core CSW register, because the mcu use psram which has cache consistency problem. but i fund the CORESIGHT_AH-
    BAPCSWDefaultSettings variables can`t config the 28 bit, user guide show it always 0. So i can`t change it .how can i change it ?

    The post was edited 3 times, last by sk.gs ().



  • I see the Arm® CoreSight™ System-on-Chip SoC-600 had use the CSW register 28 bit to config HPROT filed. just like in the picture, so the J-link can support it ?

    The post was edited 1 time, last by sk.gs ().