[SOLVED] j-link memory dump AM5728

salviador · Aug 7th 2021, 1:54pm

Ii can't dump the ram memory with the jlink jtag
CPU= TI AM5728
DDR3 RAM = 4G

I configure the jlink in the following way:

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JLink.exe -select USB -device AM5728_A15 -if cJTAG -speed adaptive

then I execute a "halt"

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halt

and then I try to read the memory

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savebin D:\test.bin 0x80000000 0x100000000

(start address memory 0x80000000
size : 0x100000000 )

but I have 0 bytes read

then i try to read only a few bytes but i always have 0 bytes read

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savebin D:\test.bin 0x80000000 0x100

how can I do a full dump of the DDR memory?

SEGGER - Alex · Aug 9th 2021, 10:48am

Hi,

Did you make sure that the DDR RAM controller is initialized, so the DDR RAM is actually accessible, at the point where you issued the "savebin" command?
DDR RAM controllers need to be initialized before any connected DDR RAM can be read/written.

I guess that issuing a "mem 0x80000000, 100" command will give you "Could not read memory", correct?
This indicates that the DDR RAM is not accessible.

BR
Alex

salviador · Aug 12th 2021, 12:21pm

I'm trying but unsuccessful,

I proceed like this:

I have to do a RAM memory dump, Linux yocto is running on the system.

In terminal:

root @ am57xx-phycore-rdk: ~ # grep "System RAM" / proc / iomem
80000000-dfffffff: System RAM
200000000-27ccfffff: System RAM

I have the correct address of the memory and now
with the jtag I make an example dump of only 0x1000 bytes length.

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Connecting to target via cJTAG
InitTarget() start
TI AM572x (Cortex-A15 core) J-Link script
J-Link script: Init ICEPick
TotalIRLen = 6, IRPrint = 0x01
InitTarget() end
TotalIRLen = 10, IRPrint = 0x0011
JTAG chain detection found 2 devices:
#0 Id: 0x3BA00477, IRLen: 04, CoreSight JTAG-DP
#1 Id: 0x2B99002F, IRLen: 06, TI ICEPick
DPv0 detected
AP map detection skipped. Manually configured AP map found.
AP[0]: AHB-AP (IDR: Not set)
AP[1]: APB-AP (IDR: Not set)
AP[2]: JTAG-AP (IDR: Not set)
Using preconfigured AP[1] as APB-AP
AP[1]: APB-AP found
Found Cortex-A15 r2p2
6 code breakpoints, 4 data breakpoints
Debug architecture ARMv7.1
Data endian: little
Main ID register: 0x412FC0F2
I-Cache L1: 32 KB, 256 Sets, 64 Bytes/Line, 2-Way
D-Cache L1: 32 KB, 256 Sets, 64 Bytes/Line, 2-Way
Unified-Cache L2: 2048 KB, 2048 Sets, 64 Bytes/Line, 16-Way
System control register:
Instruction endian: little
Level-1 instruction cache enabled
Level-1 data cache enabled
MMU enabled
Branch prediction enabled
Memory zones:
Zone: Default Description: Default access mode
Zone: AHB-AP (AP0) Description: DMA like acc. in AP0 addr. space
Zone: APB-AP (AP1) Description: DMA like acc. in AP1 addr. space
Cortex-A15 identified.
J-Link>savebin D:\test.bin 0x80000000 0x1000
Opening binary file for writing... [D:\test.bin]
Reading 4096 bytes from addr 0x80000000 into file...Not all bytes could be read from target. 0x00000000 bytes successfully read.
O.K.

Display All

but the "test.bin" file is 0 bytes !!!!

The DDR RAM controller is initialized by u-boot

SEGGER - Alex · Aug 21st 2021, 1:13am

Yes, the test.bin is 0 bytes, as J-Link Commander indicated.
It could read 0x0 bytes so the file size will be == NumBytesRead, so == 0.

We know that reading / writing memory on Cortex-A15 is working, as it is not different from an A8 or A9 in that regard.
We still suspect an MMU issue or something similar.
You can try to halt the CPU, disable the MMU via the CP15 commands in J-Link Commander and then try savebin again.
Note that disabling the MMU does not automatically flush the CPU cache, so there might be some data still be pending in the cache for write and may have not made it to the DDR yet.

BR
Alex

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