[SOLVED] STM32MP15x Cortex-M4-specific reset control using J-Link

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  • [SOLVED] STM32MP15x Cortex-M4-specific reset control using J-Link

    Hi all.

    I'm using our J-Trace Pro & J-Link Cortex-M probes to debug applications running on the Cortex-M4 core of STMicroelectronics' STM32MP15x range of SoCs.

    Debugging in engineering mode works fine since the A7 cores aren't running and we can reset the whole SoC.

    However, for debugging when starting from Linux running on the A7 cores I have to disable reset from the J-Link otherwise it resets the entire SoC which then reboots Linux and disables the M4 again.

    I would like to be able to keep the M4 core in reset but don't see any monitor commands or JLinkGDBServer command line options to do this.

    When I select "ST-LINK (OpenOCD)" in STM32CubeIDE it gives a number of available reset strategies (Connect under reset, Hardware reset, Software system reset, Core reset, None) so clearly this is doable.

    Can I create a monitor command to get the more fine-grained options using our Segger probes?
  • Hi,
    Thank you for your inquiry and sorry for the delay in response.

    You would have to implement the reset yourself via a J-Link Script file:

    Passing a J-Link script file will override the default reset.

    Best regards,
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