[ABANDONED] Cannot flash new STM32G030K6 on new design, but J-link will connect.

Yelgontin · Apr 16th 2021, 4:58pm

I have checked that the MCU is powered, and that the reset pin is not triggered.

Debug Log:
Fri Apr 16, 2021 10:46:36: Device "STM32G030K6" selected.
Fri Apr 16, 2021 10:46:36: DLL version: V7.0 , compiled Apr 8 2021 14:30:05
Fri Apr 16, 2021 10:46:36: Firmware: J-Link V10 compiled Nov 12 2020 10:06:35
Fri Apr 16, 2021 10:46:36: Selecting SWD as current target interface.
Fri Apr 16, 2021 10:46:36: JTAG speed is initially set to: 1000 kHz
Fri Apr 16, 2021 10:46:36: Found SW-DP with ID 0x0BC11477
Fri Apr 16, 2021 10:46:36: Found SW-DP with ID 0x0BC11477
Fri Apr 16, 2021 10:46:36: DPIDR: 0x0BC11477
Fri Apr 16, 2021 10:46:36: Scanning AP map to find all available APs
Fri Apr 16, 2021 10:46:36: AP[1]: Stopped AP scan as end of AP map has been reached
Fri Apr 16, 2021 10:46:36: AP[0]: AHB-AP (IDR: 0x04770031)
Fri Apr 16, 2021 10:46:36: Iterating through AP map to find AHB-AP to use
Fri Apr 16, 2021 10:46:36: AP[0]: Core found
Fri Apr 16, 2021 10:46:36: AP[0]: AHB-AP ROM base: 0xF0000000
Fri Apr 16, 2021 10:46:36: CPUID register: 0x410CC601. Implementer code: 0x41 (ARM)
Fri Apr 16, 2021 10:46:36: Found Cortex-M0 r0p1, Little endian.
Fri Apr 16, 2021 10:46:36: FPUnit: 4 code (BP) slots and 0 literal slots
Fri Apr 16, 2021 10:46:36: CoreSight components:
Fri Apr 16, 2021 10:46:36: ROMTbl[0] @ F0000000
Fri Apr 16, 2021 10:46:36: ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB4C0 ROM Table
Fri Apr 16, 2021 10:46:36: ROMTbl[1] @ E00FF000
Fri Apr 16, 2021 10:46:36: ROMTbl[1][0]: E000E000, CID: B105E00D, PID: 000BB008 SCS
Fri Apr 16, 2021 10:46:36: ROMTbl[1][1]: E0001000, CID: B105E00D, PID: 000BB00A DWT
Fri Apr 16, 2021 10:46:36: ROMTbl[1][2]: E0002000, CID: B105E00D, PID: 000BB00B FPB
Fri Apr 16, 2021 10:46:36: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:36: Reset: Reset device via AIRCR.SYSRESETREQ.
Fri Apr 16, 2021 10:46:36: Reset: SYSRESETREQ has confused core.
Fri Apr 16, 2021 10:46:36: Failed to power up DAP
Fri Apr 16, 2021 10:46:36: Reset: Using fallback: Reset pin.
Fri Apr 16, 2021 10:46:36: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:36: Reset: Reset device via reset pin
Fri Apr 16, 2021 10:46:36: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Fri Apr 16, 2021 10:46:36: Reset: Reconnecting and manually halting CPU.
Fri Apr 16, 2021 10:46:36: Failed to power up DAP
Fri Apr 16, 2021 10:46:37: CPU could not be halted
Fri Apr 16, 2021 10:46:37: Reset: Core did not halt after reset, trying to disable WDT.
Fri Apr 16, 2021 10:46:37: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:37: Reset: Reset device via reset pin
Fri Apr 16, 2021 10:46:37: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Fri Apr 16, 2021 10:46:37: Reset: Reconnecting and manually halting CPU.
Fri Apr 16, 2021 10:46:37: Failed to power up DAP
Fri Apr 16, 2021 10:46:37: CPU could not be halted
Fri Apr 16, 2021 10:46:37: Reset: Failed. Toggling reset pin and trying reset strategy again.
Fri Apr 16, 2021 10:46:37: Failed to power up DAP
Fri Apr 16, 2021 10:46:37: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:37: Reset: Reset device via AIRCR.SYSRESETREQ.
Fri Apr 16, 2021 10:46:37: Reset: SYSRESETREQ has confused core.
Fri Apr 16, 2021 10:46:38: Failed to power up DAP
Fri Apr 16, 2021 10:46:38: Reset: Using fallback: Reset pin.
Fri Apr 16, 2021 10:46:38: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:38: Reset: Reset device via reset pin
Fri Apr 16, 2021 10:46:38: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Fri Apr 16, 2021 10:46:38: Reset: Reconnecting and manually halting CPU.
Fri Apr 16, 2021 10:46:38: Failed to power up DAP
Fri Apr 16, 2021 10:46:38: CPU could not be halted
Fri Apr 16, 2021 10:46:38: Reset: Core did not halt after reset, trying to disable WDT.
Fri Apr 16, 2021 10:46:38: Reset: Halt core after reset via DEMCR.VC_CORERESET.
Fri Apr 16, 2021 10:46:38: Reset: Reset device via reset pin
Fri Apr 16, 2021 10:46:38: Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
Fri Apr 16, 2021 10:46:38: Reset: Reconnecting and manually halting CPU.
Fri Apr 16, 2021 10:46:39: Failed to power up DAP
Fri Apr 16, 2021 10:46:39: CPU could not be halted
Fri Apr 16, 2021 10:46:39: CPU could not be halted
Fri Apr 16, 2021 10:46:39: Warning: Failed to halt CPU.
Fri Apr 16, 2021 10:46:39: Hardware reset with strategy 0 was performed
Fri Apr 16, 2021 10:46:39: Initial reset was performed
Fri Apr 16, 2021 10:46:51: Unloaded macro file: C:\Program Files (x86)\IAR Systems\Embedded Workbench 8.4_2\arm\config\flashloader\ST\FlashSTM32G0xxx.mac
Fri Apr 16, 2021 10:46:52: IAR Embedded Workbench 8.50.9

Anyone have any ideas?

SEGGER - Fabian · Apr 20th 2021, 11:14am

Hi,
Thank you for your inquiry.

We are not aware of any issue with the STM32G0 devices.

According to the information of the log file, the J-Link is not able to connect to the device.
Did you make sure that the reset pin is connected on your hardware?Did this work on the same hardware before?
Does this issue also appear when connecting to the device via J-Link Commander (JLink.exe)?

Do you use custom hardware or an evaluation board? In the latter case which one?
If custom hardware, do you experience the same problem on an evaluation board?
Could you please send us a J-Link log file? How to enable:
wiki.segger.com/J-Link_DLL#Enable_J-Link_Log_File

Best regards,
Fabian

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