[SOLVED] Abstract Commands - Access Memory (RISCV) with JLink

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  • [SOLVED] Abstract Commands - Access Memory (RISCV) with JLink


    We recently purchased a JLINK Plus compact debug probe in order to attempt and debug an RV32 processor that has no System bus access Or Program Buffer but only allows memory accesses using Abstract Commands - Access Memory (as portrayed in the Debug Spec)
    As such I can successfully write/read CSRs, halt and all of the basic functionality but cannot read/write memory. If we connect OpenOCD to JLINK we are able to Load a binary and access memory successfully as expected (using riscv set_mem_access abstract)

    Unfortunately, this doesn't allow us to use Ozone, which is the main reason we purchased the probe.

    Is there a way to use such access to memory by default? If not, will it be implemented anytime soon?

  • Hello Mario,

    Can you provide a bitstream for an affordable FPGA board? (E.g. an ARTY board)

    So far, we did not have such a setup/implementation available on our desks, so it has not been implemented yet.

    The frustrating thing about the spec. is that there are many many different ways of how certain things can be supported, which makes it very complex to support it completely.
    We concentrated on the most common ones.

    By the way: We strongly recommend to have system bus access implemented, as it allows real-time variable view and using RTT (segger.com/products/debug-prob…about-real-time-transfer/) Out of my head I am not sure if that can be achieved via abstract commands as well.
  • Hi Alex,

    Thank you for your reply.

    The application we are using JLink for is an embedded IOT processor that is not yet in the market. System bus and Program buffer were not implemented to reduce the footprint of the SoC especially since, since you already implement abstract commands, abstract memory accesses are a relatively easy modification.

    I understand the frustration around the spec, but apart from checks to XLEN and some bits that need to be checked, AAM procedure is well described in sections B.7.3 p.99 and B.8.3 p.101 of the latest debug draft along with the definitions of the registers (github.com/riscv/riscv-debug-s…er/riscv-debug-stable.pdf)

    The functionality is already implemented in riscv-openOCD : github.com/riscv/riscv-openocd…/target/riscv/riscv-013.c (AC_ACCESS_MEMORY)

    As from our side, we can currently offer to assist in testing this feature in beta releases of JLink if necessary but in order to provide an FPGA build for an affordable board it will take quite some time as our use of the processor requires creating a separate build with segments of the RTL.

    Please let us know if it's possible to get this implemented as we would love to use the provided SEGGER toolset.

    Best Regards,
  • Hi,

    While I understand your point, I hope that you understand ours as well:
    We can only list as supported what we can maintain in-house.
    This means we need to have permanent access to a HW that supports it.
    I will check with the RISC-V vendors we already are partners with, if one of them probably has a bitsream with the abstract commamd memory access, but I do not think so.

    You would be welcome to provide HW if possible.

  • Hi Alex,

    Yes we are working on a FPGA build and should provide one within 2 or 3 weeks.
    This will not be a fully functional processor however, but will provide JTAG debugging and abstract commands interfaces to access CPU registers / CSRs and memory.

    We will test it by running our standard tests on it before sending it.

    Is that enough?

    We will have the bitfile generated for an ARTY board. If you need anything specific and more details please let us know.
  • Hi,

    Sorry to say that I have no idea what you are talking about.
    What is a “constraints file”?
    Actually, we are not chip / core designers, so not really heavy FPGA users.
    We do not really care about which pins you choose as the ARTY boards allow easy access to all of them :)
    Feel free to choose any pins.
  • Hello,

    We have completed and tested the bit file for ArtyA7-35. If you require another build for another FPGA module please let us know. It includes basic functionality (abstract register/memory access) for a RV32I CPU. As part of our tests we have connected to it through our PLUS compact and read and write registers successfully and the functionality for abstract memory access should be present (it will be missing functionality like single stepping and other more complex aspects).

    It includes 64KB instruction and 32KB data memories.

    Pin assignments are as follows on PMOD JA (as per reference.digilentinc.com/refe…/arty-a7/reference-manual).

    G13 TRST
    B11 TCK
    A11 TMS
    D12 TDI
    D13 TDO

    The attachment is 2.2MB so I cannot upload it here please provide another method for us to share with you the bit file.

    Best Regards,