[ABANDONED] unable to connect to target

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  • [ABANDONED] unable to connect to target

    hello
    i am trying to connect to the bitcraze ai-deck with the jlink edu mini.
    i get the following error message

    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: RISC-V
    Type '?' for selection dialog
    Device>RISC-V
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    T) cJTAG
    TIF>JTAG
    Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    JTAGConf>-1,-1
    Specify target interface speed [kHz]. <Default>: 4000 kHz
    Speed>4000
    Device "RISC-V" selected.


    Connecting to target via JTAG
    ConfigTargetSettings() start
    ConfigTargetSettings() end
    TotalIRLen = 4, IRPrint = 0x05
    JTAG chain detection found 1 devices:
    #0 Id: 0x149511C3, IRLen: 04, Custom J-Link TAP
    RISC-V behind DAP detected
    DAP error while determining CoreSight SoC version
    ConfigTargetSettings() start
    ConfigTargetSettings() end
    TotalIRLen = 4, IRPrint = 0x05
    JTAG chain detection found 1 devices:
    #0 Id: 0x149511C3, IRLen: 04, Custom J-Link TAP
    RISC-V behind DAP detected
    DAP error while determining CoreSight SoC version
    ConfigTargetSettings() start
    ConfigTargetSettings() end
    TotalIRLen = 4, IRPrint = 0x05
    JTAG chain detection found 1 devices:
    #0 Id: 0x149511C3, IRLen: 04, Custom J-Link TAP
    RISC-V behind DAP detected
    DAP error while determining CoreSight SoC version
    ConfigTargetSettings() start
    ConfigTargetSettings() end
    TotalIRLen = 4, IRPrint = 0x05
    JTAG chain detection found 1 devices:
    #0 Id: 0x149511C3, IRLen: 04, Custom J-Link TAP
    RISC-V behind DAP detected
    DAP error while determining CoreSight SoC version
    Cannot connect to target.
    J-Link>exit

    could you please explain what am i doing wrong and how can i fix it.
    regards
    rodrigo calvo
    rudiger46@yahoo.com.au
  • Hi Rodrigo,
    Thank you for your inquiry.

    The RISC-V implementation is highly configurable,
    therefore it is not guaranteed, that the J-Link is able to connect to the MCU.
    We did not yet list the GAP8 as a supported RISC-V device:
    segger.com/downloads/supported-devices.php

    So it may work or may not.

    We will add the GAP8 on our TODO,
    but we cannot provide a fixed schedule for the support implementation.

    Stay up-to-date regarding J-Link:
    segger.com/notification/subscribe.php?prodid=7,94

    Best regards,
    Fabian
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi

    I am facing issue on RISC-V E21.
    It is detecting the RISC-V behind debug port but I am getting error CPU could not be halted.
    I am able to connect to Cortex chip behind the same DAP over J-Link SWD

    I see E31 in supported devices.
  • Can you please post the log output you get?
    It obviously must be different from the first log you provided in the beginning of the thread.
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,
    regarding GAP8:
    The issue here is mainly, that we do not have any board with debug header available to implement this,
    as the Greenwave boards did not come with any debug header until now.
    If you can point us to an official evaluation board that comes with a debug header or
    if you can provide us with a custom board with a debug header, we will have a look at it.

    After receiving a board, the timeline for support would mainly depend on the used debug spec of GAP8.

    Would that be an option for you?
    If so, please contact us via our support ticket system (you can find the link in my signature, below this post).

    Best regards,
    Fabian
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.