- The trace port interface unit (TPIU) does not allow for ITM and ETM trace at the same time. The following excerpt from the Cortex-M4 Technical Reference Manual (http://infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.ddi0439b/ch11s02s02.html) discusses why:
- “When one of the two SWO modes is selected, you can enable the TPIU to bypass the formatter for trace output. If the formatter is bypassed, only the ITM and DWT trace source passes through. The TPIU accepts and discards data from the ETM. This function can be used to connect a device containing an ETM to a trace capture device that is only able to capture SWO data.”
the silicon labs post that I have quoted can be found here with more context
silicon labs references arm official documentation
I also find it strange that the functional diagram does not mention the NVIC. I thought the NVIC takes control during an exception then hands it off to the ETM. the diagram seems to imply that every exception with ETM information will branch to the ITM executable which interfaces the TPIU network stack.