[SOLVED] JLink Ultra+ JTAG/SWD Reset connections to STM32F2XX

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  • [SOLVED] JLink Ultra+ JTAG/SWD Reset connections to STM32F2XX

    I'm designing a board with a JTAG/SWD connector for use with JLink and other ICD to program and debug (not sure if SWD only will suffice).
    I've noticed that most Cortex M debuggers don't route the TRST through, instead using the MCU reset.

    Firstly, how does not being able to assert the test reset affect use of the JTAG for programming and debug?

    Secondly, I've noticed that the 19-Pin Cortex-M Adapter* optionally routes the test reset through to pin 9, as shown in the attached diagram.
    Is this standard or Segger specific?

    * segger.com/products/debug-prob…/19-pin-cortex-m-adapter/
    Images
    • reset_pipnout.png

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  • Hi,
    Thank you for your inquiry.

    For the J-Link interface description please refer to the following page:
    segger.com/products/debug-prob…gy/interface-description/

    Does this answer your question?

    Best regards,
    Fabian
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/


    Or you can contact us via e-mail.
  • Hi Fabian,
    I've already looked at that page.

    1). The line "may experience some limitations when debugging." from that page is what my first question relates to... What exactly are the limitations?
    Im asking so I may de-risk any issues with the interface for debugging.

    2). To clarify my second question; Is the connection to pin 9, as shown in my diagram, which was drawn from the page you linked, a Segger proprietary feature?
    The pin is optionally connected to what seems to be, in other implementations, a ground pin.
    Im asking as multiple people will be using the interface and they may not all gave Segger hardware.
  • Regarding my first question, ARM documentation states:

    ARM strongly recommends that both signals areseparately available on the JTAG connector. If the nRESET and nTRSTsignals are linked together, resetting the system also resets the TAPcontroller. This means that:
    - It is not possible to debug a system fromreset, because any breakpoints previously set are lost.
    - You might have to start the debug sessionfrom the beginning, because DSTREAM might not recover when the TAPcontroller state is changed.

    If anyone could help with my second question; that would be great.
  • Hi,
    The interface standard does not come from us but from Arm.
    Therefore, as long as your board is Arm standard compliant, everything should be fine.

    1) All limitations that come from not connecting the TRST signal can be found in the Arm documentation.

    2) The solder bridge on the J-Link Adapter is for support of a different interface.
    That is why we pointed you to the J-Link interface description page and not to the adapter schematics.
    Again, all adapters and interfaces we use are specified by Arm, we just provide an easy way to look them up on our website.
    There are no J-Link specific interfaces.

    Does this answer your questions?

    Best regards,
    Fabian
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/


    Or you can contact us via e-mail.
  • I can see the J-Link side is standard ARM.
    Target side and the adapter board is what Im trying to clarify.
    Ive looked in the ARM docs, thats where I found reference to the functionality but cant find anything related to those connections.

    So basically if you use the JTAG/SWD interface the test interface is left unconnected and debugging from startup is adversely affected - Is that the conclusion.
  • Hi,

    To clarify:
    If your design / MCU provides RESET and TRST they should NOT be coupled. They need to be kept separate.
    TRST is not needed by J-Link but if your MCU provides this pin and you do not forward it to J-Link, you need to make sure that it is pulled HIGH.
    If your MCU does not provide TRST, this is no problem for J-Link.

    If you are using SWD, you can ignore the TRST pin of your MCU completely.

    The TRST bridge on the SEGGER Cortex adapter is a solder option. This is because this option is non-standard (the connector usually does not specify TRST at all).


    BR
    Alex