Do we have support with J-LINK EDU for CORTEX-A53 AARCH32 mode?

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    • Do we have support with J-LINK EDU for CORTEX-A53 AARCH32 mode?

      All,
      I have a try with J-LINK EDU for cortex-A53 AARCH32 mode. But after the core is identified, the halt command failed. The target is on FPGA, so the coe run on 10MHz clock only. We have successfully debug the core with TRACE32 for quite a few months. So I think the core should be fine. See below logs
      ==========================
      Type "connect" to establish a target connection, '?' for help
      J-Link>connect
      Please specify device / core. <Default>: CORTEX-A53
      Type '?' for selection dialog
      Device>?
      Please specify target interface:
      J) JTAG (Default)
      S) SWD
      T) cJTAG
      TIF>J
      Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
      JTAGConf>
      Specify target interface speed [kHz]. <Default>: 4000 kHz
      Speed>
      Device "CORTEX-A53" selected.


      Connecting to target via JTAG
      TotalIRLen = 4, IRPrint = 0x01
      JTAG chain detection found 1 devices:
      #0 Id: 0x6BA00477, IRLen: 04, CoreSight JTAG-DP
      Scanning AP map
      AP scan stopped (required AP found)
      AP[0]: APB-AP
      Scanning ROMTbl @ 0x80000000
      [0]Comp[0] @ 0x80400000: ROM Table
      Scanning ROMTbl @ 0x80400000
      [1]Comp[0] @ 0x80410000: Cortex-A53
      [1]Comp[1] @ 0x80420000: CTI-A53
      Core found. Stopped ROM table scan: wiki.segger.com/ROMTableScan
      Cortex-A53 @ 0x80410000 (detected)
      CoreCTI @ 0x80420000 (detected)
      Debug architecture: ARMv8
      6 code breakpoints, 4 data breakpoints
      Add. info (CPU temp. halted)
      Cache info:
      Inner cache boundary: none
      LoU Uniprocessor: 0
      LoC: 0
      LoU Inner Shareable: 0
      Exception AArch usage: All: AArch32
      VMSAv8-64: Supports 48-bit VAs
      Cortex-A53 identified.
      J-Link>h

      **************************
      WARNING: CPU could not be halted
      **************************
      ==========================



      BR
      /Li.
    • New

      Hello Li,

      Thank you for your inquiry.
      Yes the A53 architecture is supported on J-Link EDU V10 or later:
      segger.com/products/debug-prob…nk/models/model-overview/

      However as the generic connect to A53 platforms rarely works you most likely need to do target specific initialization steps. You can do so using our JLinkScript interface. For more information see the J-Link user manual.

      We see that you are using a TRACE32 probe in your setup so we are not exactly sure how a J-Link EDU fits into that setup. Please note that any commercial use of the J-Link EDU is prohibited and is a license violation.
      For commercial usage at least a J-Link Base is required.
      The J-Link EDU is *not* a probe for evaluation of commercial setups. For more information about the license conditions see here:
      segger.com/products/debug-probes/j-link/models/j-link-edu/


      Best regards,

      Nino
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