Hello.
We had to add in our project LPC2132/01 FIQ interrupt handler. Due to bug in most NXP ARM based controllers, I had to disable & re enable both IRQ & FIQ bits in ARM CSPR register while refreshing CPU watchdog. Since embOS functions OS_EnableInt() / OS_DisableInt() in file OS_Priv.h only effects IRQ bit, I made my own functions which set & clear the two bits rather then only one.
My question is – how can I be sure that register r12 is free, and that it is OK to do CPSR register modifications by the help of r12 without saving it 1st to stack (this is how it is done in your code)
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Michael
We had to add in our project LPC2132/01 FIQ interrupt handler. Due to bug in most NXP ARM based controllers, I had to disable & re enable both IRQ & FIQ bits in ARM CSPR register while refreshing CPU watchdog. Since embOS functions OS_EnableInt() / OS_DisableInt() in file OS_Priv.h only effects IRQ bit, I made my own functions which set & clear the two bits rather then only one.
My question is – how can I be sure that register r12 is free, and that it is OK to do CPSR register modifications by the help of r12 without saving it 1st to stack (this is how it is done in your code)
C Source Code
- /********************************************************************
- * HAL_En_IRQ_FIQ()
- *
- * This function enable CPU IRQ (used by VIC) and FIQ interrupt
- *
- * Parameters:
- *
- * Return:
- *********************************************************************/
- __interwork __arm void HAL_En_IRQ_FIQ(void)
- {
- __asm("mrs r12,CPSR") ;
- __asm("bic r12,r12,192"); // Clear CPSR IRQ_DISABLE (bit#7), and FIQ_DISABLE (bit#6)
- __asm("msr CPSR_c,r12") ;
- }
- /********************************************************************
- * HAL_Dis_IRQ_FIQ()
- *
- * This function disable CPU IRQ (used by VIC) and FIQ interrupt
- *
- * Parameters:
- *
- * Return:
- *********************************************************************/
- __interwork __arm void HAL_Dis_IRQ_FIQ(void)
- {
- __asm("mrs r12,CPSR") ;
- __asm("orr r12,r12,192"); // Set CPSR IRQ_DISABLE (bit#7), and FIQ_DISABLE (bit#6)
- __asm("msr CPSR_c,r12") ;
- }
Michael