Hello Jim,

yes, you can use embOS spinlocks to synchronize data messaging between two or more cores.
If you have an embOS instances running on each core you usually have a shared memory in which you can pass data from one core to the other.
This shared memory must be secured with a spinlock. That's a generic way which works with every core.

But most devices have device specific mechanism to communicate between the cores like triggering an interrupt on the other core.
It depends on you application and device what works best for you.
We will create a simple spinlock sample project for the STM32H745.

Btw. We are currently working on embOS SMP implementation. With it you have one embOS instance running on all cores and you can use all existing embOS API like mailbox and queues to share data between the cores. If you don't use an affinity mask for a specific task you even don't have to care about on which core the task is currently running and it simply works.

Best regards,
Til

Please be aware this is not a technical question only but also a license/sales decision.
I can't share any details about that now (since it's simply not yet decided) but I am pretty sure we'll find a solution which will work for you.

Best regards,
Til

Something make me confused about your Software Spinlocks which I guess that they are not using atomic instructions. How can you be sure about them when the architecture support out of order execution for instructions or sometimes architectures puts a write buffer in front of memory which could cause deadlocks for synchronization mechanism ?

Maybe I could be wrong and mixing these ideas. Please Can u enlighten me ?

Best Regards
Enes

Hello Enes,

Thanks for your inquiry.

embOS spinlocks are typically implemented in assembler using atomic instructions specific to the architecture in use.
For architectures that do not support appropriate atomic instructions, however, we also offer another implementation that's completely written in "C".
For the latter, we've implemented the well-known "Lamport's bakery algorithm" (refer to research.microsoft.com/en-us/u…e/lamport/pubs/bakery.pdf for more information).

Of course, both implementations include appropriate memory and optimization barriers to account for possible memory reordering with modern microcontrollers.
Please understand, however, that this is rather a theoretical question than a question on embOS and its usage, and thus unfortunately is not covered by our support.
For further reading, e.g. on barriers on ARM Cortex-M, I'd recommend static.docs.arm.com/genc007826…ests_and_Cookbook_A08.pdf

Best regards,
Martin

Hello Martin,

Thanks for your information. I am gonna check the resources you shared.

Best Regards,
Enes