[ABANDONED] Overshoots observed on the Clock line

nikumbh · Feb 27th 2020, 5:56am

Hello,

We are using Jlink for flashing and debugging on two different MCU's from NXP. One has a working voltage of 3.3V while other has working voltage of 1.8V.

There is a considerable overshoot seen on 3.3V system of about 850mV which is much beyond the specification of the MCU. On the 1.8V system there is a overshoot of about 350mV which is slightly higher.

I have two questions. Why is the overshoot different between 3.3V and 1.8V? Why do we see much higher undershoots in 3.3V?

Please help us understand this and what can be done to bring them under specification. Please note we don't see any issue on the data lines.

Regards
Raj Nikumbh

SEGGER - Fabian · Feb 27th 2020, 2:19pm

Hi Raj,
Thank you for your inquiry.

Could you please provide us with a more specific explanation of your setup?
How exactly do you power the MCUs?
How is the J-Link connected to the MCUs?
Are you using custom Hardware or an evaluation board?

Best regards,
Fabian

nikumbh · Feb 28th 2020, 5:59am

Hi Fabian,

Thanks for your reply.

These are two different custom PCBA that we have made. The power to the MCU is generated using onboard buck regulators. Jlink is connected using a cable of about 250mm.

The setup remains similar for both 1.8V and 3.3V but there are differences in overshoots observed.

Regards
Raj Nikumbh

SEGGER - Fabian · Feb 28th 2020, 3:38pm

Hi Raj,
From what I understood, the VTreff line is overshooting, correct?
If so, the reason for the overshoot is connected to your board design/power source and not to the J-Link.

We would suggest that you revisit your board design/power source to find out what causes the overshoot.

Best regards,
Fabian

nikumbh · Mar 2nd 2020, 6:03am

Hi Fabian,

I am sorry, maybe my explanation was not correct. The overshoot is being observed on the Clock line.

Hence I was suspecting that Jlink is adding something here on when the power supply is 3.3V

Regards
Raj Nikumbh

SEGGER - Fabian · Mar 5th 2020, 6:13pm

Hi Raj,
The clock voltage uses VTref as reference.
The cause for CLK overshooting is most likely VTref being too high.

Could you please check if this is the case?
If so, you will have to adjust VTref.

Best regards,
Fabian

nikumbh · Mar 6th 2020, 11:19am

Hi Fabian,

VTRef is not having and difference as it is derived out using a buck and used onboard for other functions as well.

Regards
Raj Nikumbh

SEGGER - Fabian · Mar 19th 2020, 4:18pm

Hi Raj,
Sorry for the delay in response. Busy days...
As already mentioned, no overshoot problem is known to us.

Could you provide us with your J-Link serial number for reference?
Are you using custom cables or cables provided by SEGGER?
What target interface are you using? SWD? JTAG?...
What target device are you debugging?
Does this problem occur on an evaluation board as well?
Where exactly are you measuring the voltage with the scope? Is it directly at the chip? Where is the ground you are measuring to?
We recommend directly at the CPU at the TCK signal and use a ground signal, that is as close as possible to it.
Could you send us a recording of such a scope measurement?
Could you send us a picture of your setup?

Best regards,
Fabian

[ABANDONED] Overshoots observed on the Clock line

[ABANDONED] Overshoots observed on the Clock line

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