Using Embedded studio with a dual core STM32H745?

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    • Using Embedded studio with a dual core STM32H745?

      Hello,
      Is it possible to use Embedded Studio, and more specifically the Segger linker, to develop applications on STM32H7 dual-core processors?

      How do we inform the linker, when we compile for a core (in a project), of the space taken in the different sections by the other core (in another project, but in the same solution)?

      In the project window, which organization should we choose to organize a double core project as best as possible?

      Best regards,
      Jean-Louis
    • Hello Jean-Louis,

      see here for debugging dual core:
      STM32H745 Dual Core Development/Debugging

      Regarding the linker you can specify separate memory maps and linker files for both projects. Just make sure they do not overlap.
      More information about the linker can be found in the SEGGER Linker manual in Embedded Studio under Help->Contents->Using SEGGER Linker->SEGGER Linker user guide

      Best regards,
      Nino
      Please read the forum rules before posting: Forum Rules

      Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
      Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
      Should you be entitled to support you can contact us via our support system: segger.com/ticket/

      Or you can contact us via e-mail.
    • Hello Nino,

      "Just make sure they do not overlap" Of course ! But normally, it is precisely the role of the linker to deal with overlapping variables.

      And how do we do for common variables?
      Should each of us set its address so that they can be seen by the respective projects?

      On a big project, I fear that it represents a lot of work and is the source of many errors.

      Best regards
      Jean-Louis
    • What I expected is that there is a master project corresponding to a given core, and that the place of variables and functions of each additional core is allocated sequentially by the linker. Obviously, variables (and functions?) With the same name would be common ...Is this an unattainable dream?

      ps thanks for the links
    • Hello,

      Currently the SEGGER Linker does not offer "convenience" features for multi-core debugging so you need to take care of placement manually.
      But if you can point us to a linker that provides such features we will gladly take a look and see if they can be implemented in our linker.

      jlvern wrote:

      And how do we do for common variables?
      You would have to make sure that the "slave" project has the symbol linked to the exact address the "master" project links this symbol to.


      jlvern wrote:

      What I expected is that there is a master project corresponding to a given core, and that the place of variables and functions of each additional core is allocated sequentially by the linker. Obviously, variables (and functions?) With the same name would be common ...Is this an unattainable dream?
      It is not an unattainable dream, but it simply was/is not our core market currently so such developments do not have a high priority. But we will gladly
      put it on our feature wish list.
      If you can provide an example setup with another toolchain where such a thing is possible it would be helpful. So far we are not aware of any toolchain offering this.

      Best regards,
      Nino
      Please read the forum rules before posting: Forum Rules

      Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
      Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
      Should you be entitled to support you can contact us via our support system: segger.com/ticket/

      Or you can contact us via e-mail.
    • Hello,
      thank you for your reply

      Unfortunately, to say the least, the development of multi-core applications is not well documented.

      Among manufacturers, there is a lot, a lot, more money spent on marketing to promote the products than on documentation explaining how to use them.

      The few rare documents that we find focus on the multi-core debug, which is (perhaps) an important point, although I strongly doubt its real interest (to begin with, it would be good if the IDE did not crash not when I pass a single debugger from one heart to another - which is the case, for me, on IAR- before talking about simultaneous multi-core debug).
      st.com/content/ccc/resource/te…lations/en.DM00629855.pdf
      freertos.org/STM32H7_Dual_Core_AMP_RTOS_demo.html#DemoApp
      static.linaro.org/connect/san19/presentations/san19-102.pdf
      But these documents do not speak of what is happening at the linker level, which is however the heart of the problem.

      At Segger, you are fortunate to have mastery of the whole chain, and therefore the opportunity to do something that is a little less archaic than what is offered in others ... It seems, the reason you had developed your own linker, right?
      Basically, it doesn't seem very complicated (for basic functionality):
      - define a hierarchy in the order in which the variables associated with the core are organized in the different memories (this amounts to saying, when linking the core "n", to start arranging the variables from the location defined by the last address allocated for the core “n-1”
      - define some pragma to tell the linker if the variables (and/or functions) are common or not to different cores.

      But ... I understand that this is not a priority ... I will try to do with what I have ...
      Is it possible, in the IDE, in the options associated with the linker, to define an offset which would make it possible to shift the allocation of variables by a certain value in a given section (so as not to have to modify the MemoryMap.xml files)?

      Best regards
      Jean-Louis
    • Hello Jean-Louis,

      You are right, multi-core debug and development might be important for some, but is not of broader interest.
      However, we are taking care of this topic, and will improve multi-core debugging with J-Link, as well as multi-core application development.

      Usually, especially on embedded systems, you want to have full control and knowledge about memory (ROM and RAM) use.
      Multi-core applications are mostly similar to single-core applications. Code is in separate (Flash) regions and so is "private" data.
      The new thing is common data, used by both cores.

      The simple solution for common data is to place it at a given address and use it at that address in both cores.
      This is feasible for a small number of common variables, e.g. you put all common data in one struct.
      With the SEGGER Linker you cold also put all common variables into one section in both applications and make sure they are ordered the same way.
      This can for example be done with "place in SHARED_RAM with alphabetical order { section .common, section .common.* }; keep { section .common, section .common.* };"
      Mixing private data and common data in the same region is never recommended.

      There are a few other things to take care of, such as initializing common data only in one application.

      We might improve the SEGGER Linker in the future to export symbols in one application and make them available in the other application,
      but there is no fixed plan or roadmap for such a feature, yet.

      Regards
      Johannes