Hello,
I'm using a custom board with stm32h750xb microcontroller, a 800x480 tft display with the TM043NDH02 controller, and an external sram chip MT48LC16M16A2P-6A.
Without enable cache (using I-Cache & D-Cache)
- I can confirm the GUI_Init able to display the image correctly.
- there is some issue with performance which is a very slow during invalidation take place.
So when I enable cache, I get infinite loop stuck in 'LTDC_IRQHandler' where this interrupt function called from 'startup_stm32h750xx.s'. FYI, I have my own custom LTDC_IRQHandler function and 'without enabling the cache' it work fine with my following code during the interrupt enable.
filename: LCDConf.c
//
// Enable line interrupt
//
/* Set LTDC Interrupt callback */
BSP_IntVectSet(INT_ID_LTDC, 0, INT_IRQ, LTDC_IRQHandler);
BSP_IntEnable(INT_ID_LTDC);
_LTDC_ITConfig(LTDC_IER_LIE, ENABLE);
_NVIC_SetPriority(LTDC_IRQn, 0);
_NVIC_EnableIRQ(LTDC_IRQn);
//
// Enable DMA2D transfer complete interrupt
//
BSP_IntVectSet(INT_ID_DMA2D, 0, INT_IRQ, DMA2D_IRQHandler);
BSP_IntEnable(INT_ID_DMA2D);
_DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE);
_NVIC_SetPriority(DMA2D_IRQn, 0);
_NVIC_EnableIRQ(DMA2D_IRQn);
//
// Clear transfer complete interrupt flag
//
DMA2D->IFCR = (U32)DMA2D_IFSR_CTCIF;
Here is my finding, if I added with disable the cache and re-enable back (as shown in below code) after done setting the LTDC and DMA2D, it works fine again. I'm not sure why and what I have did wrongly in my code. As I understood, the for I/D-Cache should enable ONCE in 'main.c' with a proper configuration in 'MPU' (which I did configure a write-through for the all the SDRAM) and that's it but why I need re-enable again in 'LCDConf.c'. Now, I not sure how to proceed so mind share some light with me. Thanks.
filename: LCDConf.c
//
// Disable I/D-Cache
//
SCB_DisableICache();
SCB_DisableDCache();
//
// Enable line interrupt
//
/* Set LTDC Interrupt callback */
BSP_IntVectSet(INT_ID_LTDC, 0, INT_IRQ, LTDC_IRQHandler);
BSP_IntEnable(INT_ID_LTDC);
_LTDC_ITConfig(LTDC_IER_LIE, ENABLE);
_NVIC_SetPriority(LTDC_IRQn, 0);
_NVIC_EnableIRQ(LTDC_IRQn);
//
// Enable DMA2D transfer complete interrupt
//
BSP_IntVectSet(INT_ID_DMA2D, 0, INT_IRQ, DMA2D_IRQHandler);
BSP_IntEnable(INT_ID_DMA2D);
_DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE);
_NVIC_SetPriority(DMA2D_IRQn, 0);
_NVIC_EnableIRQ(DMA2D_IRQn);
//
// Clear transfer complete interrupt flag
//
DMA2D->IFCR = (U32)DMA2D_IFSR_CTCIF;
//
// Enable I/D-Cache and flush the D-Cache
//
SCB_CleanDCache();
SCB_EnableICache();
SCB_EnableDCache();
I'm using a custom board with stm32h750xb microcontroller, a 800x480 tft display with the TM043NDH02 controller, and an external sram chip MT48LC16M16A2P-6A.
Without enable cache (using I-Cache & D-Cache)
- I can confirm the GUI_Init able to display the image correctly.
- there is some issue with performance which is a very slow during invalidation take place.
So when I enable cache, I get infinite loop stuck in 'LTDC_IRQHandler' where this interrupt function called from 'startup_stm32h750xx.s'. FYI, I have my own custom LTDC_IRQHandler function and 'without enabling the cache' it work fine with my following code during the interrupt enable.
filename: LCDConf.c
//
// Enable line interrupt
//
/* Set LTDC Interrupt callback */
BSP_IntVectSet(INT_ID_LTDC, 0, INT_IRQ, LTDC_IRQHandler);
BSP_IntEnable(INT_ID_LTDC);
_LTDC_ITConfig(LTDC_IER_LIE, ENABLE);
_NVIC_SetPriority(LTDC_IRQn, 0);
_NVIC_EnableIRQ(LTDC_IRQn);
//
// Enable DMA2D transfer complete interrupt
//
BSP_IntVectSet(INT_ID_DMA2D, 0, INT_IRQ, DMA2D_IRQHandler);
BSP_IntEnable(INT_ID_DMA2D);
_DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE);
_NVIC_SetPriority(DMA2D_IRQn, 0);
_NVIC_EnableIRQ(DMA2D_IRQn);
//
// Clear transfer complete interrupt flag
//
DMA2D->IFCR = (U32)DMA2D_IFSR_CTCIF;
Here is my finding, if I added with disable the cache and re-enable back (as shown in below code) after done setting the LTDC and DMA2D, it works fine again. I'm not sure why and what I have did wrongly in my code. As I understood, the for I/D-Cache should enable ONCE in 'main.c' with a proper configuration in 'MPU' (which I did configure a write-through for the all the SDRAM) and that's it but why I need re-enable again in 'LCDConf.c'. Now, I not sure how to proceed so mind share some light with me. Thanks.
filename: LCDConf.c
//
// Disable I/D-Cache
//
SCB_DisableICache();
SCB_DisableDCache();
//
// Enable line interrupt
//
/* Set LTDC Interrupt callback */
BSP_IntVectSet(INT_ID_LTDC, 0, INT_IRQ, LTDC_IRQHandler);
BSP_IntEnable(INT_ID_LTDC);
_LTDC_ITConfig(LTDC_IER_LIE, ENABLE);
_NVIC_SetPriority(LTDC_IRQn, 0);
_NVIC_EnableIRQ(LTDC_IRQn);
//
// Enable DMA2D transfer complete interrupt
//
BSP_IntVectSet(INT_ID_DMA2D, 0, INT_IRQ, DMA2D_IRQHandler);
BSP_IntEnable(INT_ID_DMA2D);
_DMA2D_ITConfig(DMA2D_CR_TCIE, ENABLE);
_NVIC_SetPriority(DMA2D_IRQn, 0);
_NVIC_EnableIRQ(DMA2D_IRQn);
//
// Clear transfer complete interrupt flag
//
DMA2D->IFCR = (U32)DMA2D_IFSR_CTCIF;
//
// Enable I/D-Cache and flush the D-Cache
//
SCB_CleanDCache();
SCB_EnableICache();
SCB_EnableDCache();