[ABANDONED] RISCV base timing information

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  • [ABANDONED] RISCV base timing information

    Respected sir,
    I am the new user of the Segger Embedded Studio, but the tool is superb as it is flexible for the beginners.
    I have executed the C application code using RISCV-ISA RV32IMAF and obtained the results.

    Based on which core, the base timing information is designed for obtaining the cycle count. Please provide the details regarding the base timing information of floating point instructions of RV32IMAF

    Kindly suggest in this regard
  • Hello,

    Thank you for your inquiry.
    Could you elaborate what cycle count you are referring to?
    Currently Embedded Studio does not implement a cycle counter display for RISC-V.
    If you use a simulator project instead running on actual hardware we display a cycle counter at the bottom as in the simulation we have full control about the execution so we know exactly how many cycles have been run.

    Best regards,
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