[SOLVED] J-Link Debugging the R5 core on the Xilinx Ultrascale+ XCZU7EV7

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  • [SOLVED] J-Link Debugging the R5 core on the Xilinx Ultrascale+ XCZU7EV7

    I am attempting to do a debug session on the arm R5_0 core of an Ultrascale+ XCZU7EV7 using a Jlink Plus and, so far, have had no luck getting it to work.

    My setup:
    • Xilinx ZCU104 Ulrascale+ evaluation board
      • SW6 is set to Jtag mode (on, on, on, on)
    • J-Link plus running Firmware version V10.10
      • Connected to the ZCU104 via flywires to a 14pin adapter connected to J180
    • Ozone debugger, or Eclipse GDB SEGGER J-Link Debugging
    Whenever I start a debug session I it seems to get as far as writing the app to memory before the failures start to happen. Ozone will loose connection while writing to memory, and Eclipse complains about memory read failures but doesn't disconnect and ends up deep in the weeds.

    I've attached the debug logs from both Ozone and Eclipse and any information as to how to resolve this problem would be greatly appreciated.

    Debugging the ZCU104 works as expected with the Xilinx SDK and the Xilinx debug cable, but we are trying to move our project away from being locked to the Xilinx SDK and use CMAKE instead.

    Thank you
  • After further evaluation, the memory access problems are due to the Ultrascale+ XCZU7EV7 DDR memory requiring a init procedure before it can be accessed. I'm working on creating a jlink init script using the Xilinx SDK's init process as a guide. Once I figure out the jlink equivalent init sequence I'll post a copy of the script here.
  • Hello,

    Thank you for your inquiry.
    As you correctly found out the target DDR init has to be executed on such devices first so it is accessible by the debug probe.
    This can be done using the JLinkScript and e.g script function SetupTarget().
    Please understand that we can't assist you in this as board specific initialization is user responsibility.

    Best regards,
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