[SOLVED] Flashing nonsecure region on Cortex m23 is failing (Writing target memory failed)

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  • [SOLVED] Flashing nonsecure region on Cortex m23 is failing (Writing target memory failed)

    I am developing against a Nuvoton m2351 via their NuMaker PFM-M2351 board and trying to use a J-Link Base to flash both the secure and nonsecure regions. The .hex images flash properly when using the built-in Nu-Link-Me ICE bridge.

    I have the secure and nonsecure regions partitioned out to evenly split available flash (256k each). Secure gets written to 0x0 without problems, but the nonsecure image fails because it is being written to 0x10040000 which is the nonsecure region (nonsecure region bit is set). Of course this board only has 512k of flash so the segger complains that it can't write to that address. If I remove the nonsecure region bit (0x00040000), it writes properly but the secure image doesn't recognize there is nonsecure code to jump to after booting.

    Is there support for writing non-secure regions in the J-Link that I'm missing? Below is the j-link flash session.

    Thank you!

    Source Code

    1. $ JLinkExe -if SWD -device M2351KIAAE -speed 10000 -ExitOnError 1 -CommandFile flash.jlinkscript
    2. SEGGER J-Link Commander V6.50a (Compiled Aug 26 2019 10:26:37)
    3. DLL version V6.50a, compiled Aug 26 2019 10:26:25
    4. J-Link Commander will now exit on Error
    5. J-Link Command File read successfully.
    6. Processing script file...
    7. J-Link connection not established yet but required for command.
    8. Connecting to J-Link via USB...O.K.
    9. Firmware: J-Link V10 compiled Aug 12 2019 10:37:43
    10. Hardware version: V10.10
    11. S/N: 50101333
    12. License(s): GDB
    13. VTref=3.277V
    14. Device "M2351KIAAE" selected.
    15. Connecting to target via SWD
    16. Found SW-DP with ID 0x0BF11477
    17. Scanning AP map to find all available APs
    18. AP[1]: Stopped AP scan as end of AP map has been reached
    19. AP[0]: AHB-AP (IDR: 0x04770025)
    20. Iterating through AP map to find AHB-AP to use
    21. AP[0]: Core found
    22. AP[0]: AHB-AP ROM base: 0xE00FE000
    23. CPUID register: 0x411CD200. Implementer code: 0x41 (ARM)
    24. Found Cortex-M23 r1p0, Little endian.
    25. FPUnit: 4 code (BP) slots and 0 literal slots
    26. Security extension: implemented
    27. Secure debug: enabled
    28. CoreSight components:
    29. ROMTbl[0] @ E00FE000
    30. ROMTbl[0][0]: E00FF000, CID: B105100D, PID: 000BB4CB ROM Table
    31. ROMTbl[1] @ E00FF000
    32. ROMTbl[1][0]: E000E000, CID: B105900D, PID: 000BBD20 Cortex-M23
    33. ROMTbl[1][1]: E0001000, CID: B105900D, PID: 000BBD20 DWT
    34. ROMTbl[1][2]: E0002000, CID: B105900D, PID: 000BBD20 FPB
    35. ROMTbl[1][5]: E0041000, CID: B105900D, PID: 001BBD20 Cortex-M23
    36. ROMTbl[0][1]: E0040000, CID: B105900D, PID: 000BBD20 Cortex-M23
    37. Cortex-M23 identified.
    38. PC = 3000C002, CycleCnt = 00000000
    39. R0 = 00000000, R1 = 3000C000, R2 = 3000C000, R3 = 3000C000
    40. R4 = 3000C000, R5 = 3000C000, R6 = 3000C000, R7 = 3000C000
    41. R8 = 3000C000, R9 = 3000C000, R10= 3000C000, R11= 3000C000
    42. R12= 3000C000
    43. SP(R13)= 3000C200, MSP= 3000C200, PSP= FFFFFFFC, R14(LR) = FEFFFFFF
    44. XPSR = 31000000: APSR = nzCVq, EPSR = 01000000, IPSR = 000 (NoException)
    45. CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
    46. Security extension regs:
    47. MSP_S = 20001660, MSPLIM_S = 00000000
    48. PSP_S = FFFFFFFC, PSPLIM_S = 00000000
    49. MSP_NS = 3000C200, MSPLIM_NS = 00000000
    50. PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000
    51. CONTROL_S = 00, FAULTMASK_S = 00, BASEPRI_S = 00, PRIMASK_S = 00
    52. CONTROL_NS = 00, FAULTMASK_NS = 00, BASEPRI_NS = 00, PRIMASK_NS = 00
    53. FPU regs: FPU not enabled / not implemented on connected CPU.
    54. Reset delay: 0 ms
    55. Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
    56. Reset: Halt core after reset via DEMCR.VC_CORERESET.
    57. Reset: Reset device via AIRCR.SYSRESETREQ.
    58. PC = 0000116C, CycleCnt = 00000000
    59. R0 = FFFFFFFF, R1 = FFFFFFFF, R2 = FFFFFFFF, R3 = FFFFFFFF
    60. R4 = FFFFFFFF, R5 = FFFFFFFF, R6 = FFFFFFFF, R7 = FFFFFFFF
    61. R8 = FFFFFFFF, R9 = FFFFFFFF, R10= FFFFFFFF, R11= FFFFFFFF
    62. R12= FFFFFFFF
    63. SP(R13)= 20001698, MSP= 20001698, PSP= FFFFFFFC, R14(LR) = FFFFFFFF
    64. XPSR = 01000000: APSR = nzcvq, EPSR = 01000000, IPSR = 000 (NoException)
    65. CFBP = 00000000, CONTROL = 00, FAULTMASK = 00, BASEPRI = 00, PRIMASK = 00
    66. Security extension regs:
    67. MSP_S = 20001698, MSPLIM_S = 00000000
    68. PSP_S = FFFFFFFC, PSPLIM_S = 00000000
    69. MSP_NS = FFFFFFFC, MSPLIM_NS = 00000000
    70. PSP_NS = FFFFFFFC, PSPLIM_NS = 00000000
    71. CONTROL_S = 00, FAULTMASK_S = 00, BASEPRI_S = 00, PRIMASK_S = 00
    72. CONTROL_NS = 00, FAULTMASK_NS = 00, BASEPRI_NS = 00, PRIMASK_NS = 00
    73. FPU regs: FPU not enabled / not implemented on connected CPU.
    74. Downloading file [secure/secure.hex]...
    75. Comparing flash [100%] Done.
    76. Erasing flash [100%] Done.
    77. Programming flash [100%] Done.
    78. Verifying flash [100%] Done.
    79. J-Link: Flash download: Bank 0 @ 0x00000000: 1 range affected (10240 bytes)
    80. J-Link: Flash download: Total time needed: 0.990s (Prepare: 0.003s, Compare: 0.397s, Erase: 0.466s, Program: 0.081s, Verify: 0.039s, Restore: 0.002s)
    81. O.K.
    82. Downloading file [nonsecure/nonsecure.hex]...
    83. Writing target memory failed.
    84. Script processing completed.
    Display All
  • Hi uncleskippy,

    the flash memory controller of the Nuvoton M2351 series device can only write and erase addresses within the secure address range of the flash.
    Addressing flash into a non-secure area results in a programming error.
    So you need to program your non-secure hex-file into the secure address area, too.
    According to your settings that the second flash bank is defined as non-secure area, you will find your data starting at 0x1004 0000 and not at 0x0004 0000.

    Best regards,
    Sebastian