Need output in Verilog format

    This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

    • Hello,

      Thank you for your inquiry.
      Could you elaborate what exactly you are trying to do?
      We do not provide any Keil tools as Keil is a different company.

      If you are looking to do some pre or post compile/build steps you can do so in Embedded Studio project settings where you can e.g. call external CL applications which will then be executed at the hook points that you have set in your project.

      Best regards,
      Nino
      Please read the forum rules before posting: Forum Rules

      Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
      Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
      Should you be entitled to support contact us per e-mail.
      Alternatively our support system can be used as well: segger.com/ticket/