[SOLVED] J-Trace and 4 bit TRACE on IMXRT1021

dmarples · Jul 9th 2019, 11:18pm

Hi there,

I'm trying to do parallel trace on an IMXRT1021 144 pin variant. I can only seem to get it to work for 1-bit wide tracing. When I try to set 4 bit (either via Ozone GUI or using a JLinkScript file with the line JLINK_TRACE_PortWidth = 4) I still only see single bit output from the chip (i.e. TRACECLK and TRACE0 are toggling) and, in this circumstance, I get no trace output.

Is there something I'm missing here? I have setup the pins manually to support trace (ALT6 mode) with no difference in symptom. There is nothing else contending for the pins.

Regards

DAVE

SEGGER - Nino · Jul 10th 2019, 10:25am

Hello Dave,

Thank you for your inquiry.
Could you provide the S/N of your J-Trace for reference?
Generally we try to provide as many trace examples for trace capable target devices as possible. However one key prerequisite is that the trace lanes are available on a public eval board.
segger.com/products/debug-prob…echnology/tested-devices/
This is unfortunately not the case for the iMXRT10xx series so far.

But if you are interested I could provide you with the JLinkScript source for the iMXRt105x series. wiki.segger.com/Tracing_on_NXP…050_Trace_Reference_Board)

This chip uses slightly different pins for tracing than the RT1021 but the principle should be the same and this way you would have a working template to reference from.
Would that be of interest to you?

Best regards,
Nino

dmarples · Jul 10th 2019, 10:33am

Hi Nino,

This is our own board and we've specifically brought out the trace pins to be able to use with the JTrace....which is a bit of a pain as they're shared with the Ethernet.

I've PMed you my s/n and email address. If you could send me the source that equates to the PEX file for the 1050 that would be very helpful.

What concerns me slightly is that in the TPIU registers (TPIU_SSPSR) it would seem that only one bit tracing is supported on this chip...so I'm hoping I'm mis-reading them. I've got a question in with NXP on this point, as all of their documentation suggests four bit trace should be available.

Regards

DAVE

SEGGER - Nino · Jul 10th 2019, 11:23am

Hi Dave,

dmarples wrote:

which is a bit of a pain as they're shared with the Ethernet.

Yeah this is why we created our own trace reference board for the iMXRT105x series as the NXP eval boards did not provide any approach to demonstrate the trace feature which is quite unfortunate.

I sent you the download link for the script via PM now.

dmarples wrote:

What concerns me slightly is that in the TPIU registers (TPIU_SSPSR) it would seem that only one bit tracing is supported on this chip...so I'm hoping I'm mis-reading them.

That sounds strange, what value do you get? If the value is >= 0xF 4 bit trace should be supported.

Best regards,
Nino

dmarples · Jul 10th 2019, 11:44am

I get 1

AFAIK there's nothing special I have to do in order to be able to _read_ from the TPIU....

Regards
DAVE

SEGGER - Nino · Jul 10th 2019, 3:28pm

Hi Dave,

This is odd indeed. Lets pretend NXP simply programmed a wrong value there

Would not be the first time we see incorrect read only register values.

Best regards,
Nino

[SOLVED] J-Trace and 4 bit TRACE on IMXRT1021

[SOLVED] J-Trace and 4 bit TRACE on IMXRT1021

dmarples wrote:

dmarples wrote:

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