[SOLVED] "RISC-V behind a DAP": more info please

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  • [SOLVED] "RISC-V behind a DAP": more info please

    The V6.46h J-Link release notes make multiple mentions of "RISC-V behind a DAP as setup" / "RISC-V behind a DAP setups" / "RISC-V behind a DAP as setup". It suggests RISC-V debug is now feasible through an ARM DAP, including via SWD.

    Is this a RISC-V debug interface memory mapped into a CoreSight bus, or something else?

    What are the vendor and part number(s) for the implementation that Segger now supports?

    Where is the specification for how RISC-V debug is implemented "behind a DAP"?

  • Hello,

    Thank you for your inquiry.
    The RISC-V behind a DAP integration has been created in cooperation with some silicon vendors who chose to combine both ARM and RISC-V in one design.
    However for such a setup there is no official specification and is a custom integration on a per case basis.
    The documentation for the implemented interfaces is the silicon vendors IP so we are not allowed to share that information.
    So unfortunately we can't provide additional information in this regard.

    Best regards,
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