Failure to program Renesas S5: CPU in reset forever/TDO always high

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    • Failure to program Renesas S5: CPU in reset forever/TDO always high

      I'm trying to wake up and program a blank Renesas Synergy S5D9 using JLink. The setup should be good as I successfully connected and programmed the demo board from Renesas ("PK").

      Steps taken:

      1) Connected JLink to PK board. Connected as expected, able to load program.

      2) Transferred JLink wires (no header) directly over to our S5 board.

      2a) Tried JFlash Lite. Erase command returned "Could not erase", program command returned "Could not download".

      2b) Tried JLink Commander, both JTAG and SWD (system responses below). Used default clock of 4000 kHz and 10 kHz clock (because of long wires used), same results for each.

      For JTAG:
      As shown in error messages "TDO is constant high" repeated.
      Do not understand this- checked TDO with DVM and it was high (3.3V). Disconnected wire from JLink and found that pin was low, signal from JLink was high. So JLink is complaining about problem it causes?

      For SWD:
      Erase command failed.
      Halt command returned "Cannot halt CPU".
      Tried "reset" and got result below where it says device is in "reset forever". Same message whether JLink connected or not to RESET pin of S5.

      [b]Any suggestions to resolve this issue?[/b]

      Thanks for help!

      _________________________________________________________________
      JTAG:
      Device "R7FS5D97E" selected.

      Connecting to target via JTAG
      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.

      ****** Error: SC32 (connect): Cannot connect to CPU.

      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.
      Could not measure total IR len. TDO is constant high.

      ****** Error: SC32 (connect): Cannot connect to CPU.

      Cannot connect to target.
      J-Link>

      _________________________________________________________________

      SWD:
      J-Link>r
      Reset delay: 0 ms
      Reset type NORMAL: Resets core & peripherals via SYSRESETREQ & VECTRESET bit.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via AIRCR.SYSRESETREQ.
      Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
      Reset: Using fallback: Reset pin.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via reset pin
      Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
      Reset: Reconnecting and manually halting CPU.
      Found SW-DP with ID 0x5BA02477
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.

      **************************
      WARNING: CPU could not be halted
      **************************

      Reset: Core did not halt after reset, trying to disable WDT.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via reset pin
      Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
      Reset: Reconnecting and manually halting CPU.
      Found SW-DP with ID 0x5BA02477
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.

      **************************
      WARNING: CPU could not be halted
      **************************

      Reset: Failed. Toggling reset pin and trying reset strategy again.
      Found SW-DP with ID 0x5BA02477
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via AIRCR.SYSRESETREQ.
      Reset: S_RESET_ST never gets cleared. CPU seems to be kept in reset forever.
      Reset: Using fallback: Reset pin.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via reset pin
      Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
      Reset: Reconnecting and manually halting CPU.
      Found SW-DP with ID 0x5BA02477
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.

      **************************
      WARNING: CPU could not be halted
      **************************

      Reset: Core did not halt after reset, trying to disable WDT.
      Reset: Halt core after reset via DEMCR.VC_CORERESET.
      Reset: Reset device via reset pin
      Reset: VC_CORERESET did not halt CPU. (Debug logic also reset by reset pin?).
      Reset: Reconnecting and manually halting CPU.
      Found SW-DP with ID 0x5BA02477
      AP map detection skipped. Manually configured AP map found.
      AP[0]: AHB-AP (IDR: Not set)
      AP[0]: Core found
      AP[0]: AHB-AP ROM base: 0xE00FF000
      CPUID register: 0x410FC241. Implementer code: 0x41 (ARM)
      Found Cortex-M4 r0p1, Little endian.

      **************************
      WARNING: CPU could not be halted
      **************************

      J-Link>