Hi
Now,I'm currently validating IP about cortex-A7 with FPGA. I can connect to core0 of the cpu by JLINK, but not connect to core1.
The JLINK version is V9. Like this,core1 defaults to halt as long as it be connected to JLINK.
How to debug cores other than core0 using JLINK,or mulit-core debugging is not supported.
Thanks
Now,I'm currently validating IP about cortex-A7 with FPGA. I can connect to core0 of the cpu by JLINK, but not connect to core1.
The JLINK version is V9. Like this,core1 defaults to halt as long as it be connected to JLINK.
How to debug cores other than core0 using JLINK,or mulit-core debugging is not supported.
Thanks