[SOLVED] PC of target system has unexpected value after programming sector

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  • [SOLVED] PC of target system has unexpected value after programming sector

    Hello,

    i've get this error while trying to read a Flash (S29GL512N) attached to the EMIFS interface of an OMAP5912 (ARM9 based) using J-Flash.
    It aborts after reading 20 or 30 sectors with the error shown here:



    If i get it right, the J-Flash emitts a reader-helper (RAM code) into the SRAM of the OMAP and sets program counter (PC) to execute it.
    This RAM code reads sectors from the Flash chip into the SRAM and transfers it via the JTAG line to the host running J-Flash.
    Also it seems that J-Flash checks the program counter (PC) after each transferred sector, to ensure the RAM-code is still alive.
    When the issue occures the PC seems to be start boot-address, as if anything has reset the OMAP.

    Could you tell more about how the error is detected and what the register contents could tell me to narrow down the source of the problem?
    Can i look into the RAM code somewhere?

  • Hello,

    Thank you for your inquiry.
    The OMAP5912 is not officially supported by J-Link so I assume you are using your own Flash loader at this point.
    segger.com/downloads/supported-devices.php
    In our open Flash loader Wiki article you can find some troubleshooting information regarding the unexpected PC value issue:
    wiki.segger.com/Adding_Support…alue_after_flash_download

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • I see, thanks. It seems that there is something missing on halting the system for Jtag access (watchdog, etc.) so the RAM code get's interrupted. How can i add some extra register settings i suspect? Or better, what excatly does the HALT and the Disable MMU command from the J Flash init procedure do/send to the chip? This i can compare with the settings i think is right and add the missing commands?

    And another question is driving me mad: How can prevent the chip from executing bootcode after poweron, so i had enough time to init JTAG HALT?

  • Hello,

    All default behaviour of the J-Link debug logic can be customized with a JLinkScript file. More information can be found in the J-Link user manual UM08001.

    elektroll wrote:

    And another question is driving me mad: How can prevent the chip from executing bootcode after poweron, so i had enough time to init JTAG HALT?
    Good question. The answer is unfortunately that it depends on how it is implemented chip specific. For Cortex-M reset behaviour is defined by Arm and can be implemented generic.
    For old ARM cores or Cortex-A/R it is usually not defined and chip/vendor specific. In that case we suggest getting in contact with the silicon vendor or consult the chips reference manual and implement the suggested steps using a JLinkScript file.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.