[SOLVED] JTrace PRO No Trace on Custom Board. Yikes!

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  • [SOLVED] JTrace PRO No Trace on Custom Board. Yikes!

    We are attempting to trace a custom board with a Zynq 7020device using JTrace Pro and Ozone. We have enabled the ETM using 4 trace datapins at 75MHz (trace clock) from the ARM core(s) in the Zynq device. We haveconnected the 4 trace data lines, trace clock and JTAG as described in (many)app notes. The trace signals go through the FPGA fabric and use the EMIO. Ozoneis able to connect to the device, halt it, restart it, display memory, step instructionsbut no trace data is produced.

    When the application if running under Ozone, the traceindicator LED is red. When the application is halted, the trace indicator LEDis green. I have tried using JTrace through USB and Ethernet and the behavior isthe same.

    The webserver trace status indicates:
    Trace clock: 74990kHz
    Half-syncdetection: 0xFFF7FFFF (Not O.K. nohalf-sync pattern detected)
    Last incorrect half-syncsampled: 0xFFF7FFFF
    Changing the delay has no beneficial effect. The trace clockswitches between 75000 kHz and 74990 kHz
    The half sync detection occasionally changes to 0xF7F7FFFFor 0xFF7FFFFF if I adjust the timing while the application is running. If theapplication is not running the value never changes.

    We are kind of at our wit’s end here and would appreciatesome direction to get trace working? Am I forgetting something in the Ozonesetup? Could it be a Zynq setup issue?

    Running the tutorial and the trace demo board works just fine.

    We are using the very latest Ozone, JLink and JTrace firmware.

    Any thoughts would be appreciated
  • Hello,

    Thank you for your inquiry.
    Generally tracing with Cortex-A9 is supported by J-Trace PRO so the described issue is most likely related to an incorrect/incomplete trace init. (But getting any trace clock is already a good step in the right direction ;) ). How to use a JLinkScript for that task is described here for Cortex-M: wiki.segger.com/How_to_configu…t_files_to_enable_tracing
    Unfortunately there are currently no eval boards available on the market with a Zynq 7020 that would have the trace pins connected to the trace interface so unfortunately we can't provide you with a generic init at the moment for that particular device. Would it be possible for you to provide us with your custom board so we could try to implement an example init using your board?

    I believe you have been in contact with Axel as well. If you prefer you can follow up with him as well if you don't want to risk exposing critical information in this public forum.

    Best regards,
    Nino
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Nino,

    Thanks for your response. The zc702 board (xilinx.com/products/boards-and-kits/ek-z7-zc702-g.html) has a 7020 on it and with the purchase of the XM105 FMC card (xilinx.com/support/documentation/boards_and_kits/ug537.pdf) it is possible to route the trace pins out through the EMIO to the FMC card pins and connect a trace cable (xilinx.com/support/answers/46915.html). Our custom board is similar to that. We use 4 EMIO pins as our trace pins and route the trace clock through the fabric to the IO as well. This functionality should in no way effect the trace set up. The only potential complexity I see is setting up the "funnel" connection properly to collect trace information from either or both ARM cores.

    While providing an actual init sequence may be difficult or beyond the call of duty for you or your team, a few hints and pointers - specifically related to setting up the funnel - would be helpful.

    The post was edited 2 times, last by neil.photonics ().

  • Hello,

    Thank you for the additional information.
    We will try to order such a debug card for the zc702 board (which we actually have in house).
    If possible we will then generate a generic setup as we did for our remaining tested devices: segger.com/products/debug-prob…echnology/tested-devices/

    How are you currently initializing the the target device specific trace init (e.g. pins, trace clocks etc)?
    Through your application/bootloader or a JLinkScriptFile?
    We recommend using a JLinkScriptFile for maximum flexibility and portability.
    Additionally a couple of month ago we expanded the customization options for the generic trace init that usually the J-Link DLL will execute.
    In the J-Link User Guide you will find JLinkScript functions e.g. StartTF() and StopTF() which will replace the generic handling of the DLL.
    Generic here means that we assume it is a single core device and trace funnel port 0 and 1 is to be used and that the Coresight modules are accessible by the debug/trace probe over the same debug AP as the target core.
    This is usually true for about 98% of trace capable devices on the market, but for more "special" devices especially Cortex-A and -R series things get more and more none generic.

    I hope some of these hints help you with your setup. In the meantime we will try to get our own setup up and running.

    Best regards,
    Nino
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hello,

    Thank you for your feedback.
    To keep all information in one place this thread will be closed now.
    Could you open a ticket (see my signature) so the request can be tracked more easily by us?

    Best regards,
    Nino
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.