[SOLVED] STM32F769I-EVAL J-Flash QSPI Programming Issues

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  • [SOLVED] STM32F769I-EVAL J-Flash QSPI Programming Issues

    Hi

    We’re having issues programming the external QSPI flash chip of the STM32F769I-EVAL board.

    We’ve followed the guide found in the wiki, wiki.segger.com/STM32F769I_EVAL, and tried to load the “STM32CubeDemo_STM32F769I-EVAL_V1.3.0.hex” file found in STM cube via J-Flash but the QSPI code section seems to fail verification 9 out of 10 times. The eval board seems ok and will program fine with st-link (using the external loader option) and the inbuilt programmer.

    I’ve attached the xml and jflash file for checking and can confirm that the elf file is in the same directory.

    Thanks

    Phil
    Files
  • Hello,

    Thank you for your inquiry.
    Such an issue is not known to us.
    Which J-Link software version are you currently using?
    Could you provide a J-Link log file of the failing session?
    wiki.segger.com/Enable_J-Link_log_file
    Could you also provide the .hex file for reproduction purposes?

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hello,

    Thank you for providing the reproducer.
    With it we were able to reproduce the reported issue.
    Attached you can find a improved version of the flash loader.
    Could you test it with the attached version?
    Make sure to erase the whole chip before reprogramming it.

    Best regards,
    Nino
    Files
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    Unfortunately it still seems to be failing the verification, I've attached the log.

    When you say erase the whole chip I'm assuming you mean setting the erase -> chip option in the production tab of the project settings?

    Many Thanks
    Files
    • JLinkARM-New.zip

      (232.6 kB, downloaded 287 times, last: )
  • Hello,

    pweberlth wrote:

    When you say erase the whole chip I'm assuming you mean setting the erase -> chip option in the production tab of the project settings?
    Target Manual Programming-> Erase Chip
    To program use Target-> Manual Programming-> Program & Verify
    We just retested the modified loader and we always get the attached result that verification was successfull and the STemWin demo runs perfectly.
    From the log it seems that you are not using the newly provided flash loader but still the old one instead.
    How did you set which flash loader to use? Did you place both the JLinkDevices.xml and the flash loader elf in the J-Link software installation folder where the JFlash.exe is located?

    Best regards,
    Nino
    Images
    • Capture.PNG

      8.2 kB, 466×403, viewed 369 times
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi,

    I've just re-downloaded your new file again, placed it in the folder with the exe. I haven't touched the xml file as the new elf file name hasn't changed from the wiki post one.

    Run J-flash as per your last post, and were still seeing a verification error.

    As I stated in my first post, It does work occasionally but most of the time it fails. The only way we've been able to get it to program consistently with J-Flash is to erase the whole chip via st-link first.

    I've attached 3 logs all with the new elf file, one passing, one failing and one with ST Link erase first

    Many Thanks

    Phil
    Files
  • Hello,

    We investigated further and found that the ST example project reconfigures the SPI controller to use 4-byte address space instead of 3 which J-Link expects.
    This leads to weird shifts when using our flash loader.
    With "normal" applications this should not happen.
    For reference if you delete the application in internal RAM which does the reconfiguration and only try to verify the external flash it will work everytime. But if the main application reconfigured that setting at least once it will not work and need a power on reset.
    We will see if a workaround/detection can be implemented for such cases.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Nino,

    We’ve investigated our options and unfortunately, we cannot work in 3-byte address mode as that would make it very difficult to access the higher (greater than 128Mb) areas of the flash chip using the easier STM32 FMC memory mapped mode.

    We have managed to implement a hardware work around for using your flash loader when programming the QSPI chip below 128Mb. It would appear that it does not send a reset instruction as part of the qspi init routine, and so the qspi chip is left in whatever mode was previously running on it.

    To work round this we’ve now connected the unused reset pin of the qspi chip to eval board’s reset line which seems to fix the programming of the qspi chip below 128Mb but above that we still have a verify error.

    Thanks for your help
    Phil
  • Hi Phil,

    Great to hear that you found a workaround for your setup.
    We will consider this thread as closed now.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.