[ABANDONED] Custom script to connect J-Flash/J-LinkCommander to OMAP5948 and read attached S29GLxxx flash

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  • [ABANDONED] Custom script to connect J-Flash/J-LinkCommander to OMAP5948 and read attached S29GLxxx flash

    Hello,

    because this MPU is not directly supported by Segger J-Link i searched the net for solutions and found a connectionscript for an other JTAG Interface here: download.ronetix.info/peedi/cfg_examples/arm9/omap5948.cfg
    Now i wonder if it could be "translated" to Segger script language.

    I started with J-Flash (v6.x) where i use "ARM9" as architecture (which the OMAP5948 is) and added "Halt" and "Disable MMU" commands in init steps. Set init-speed to "Adaptive" and pre-init-speed to "Auto". With this setup i manage to read single sectors from flash. But as i try to read more, the CPU shuts down. I guess i ran into an watchdog issue.
    This is, where the above script comes into account, because there is some watchdog handling.


    Source Code

    1. [INIT_OMAP5948]
    2. ; reset ARM
    3. set cpsr 0x000000D3 ; set supervisor mode
    4. set pc 0x00000000
    5. set control 0x00050078 ; CP15 Control : disable caches
    6. ; disable ARM9 Watchdog Timer
    7. mem write 0xFFFEC808 0x00F5 ; convert WD timer into GP timer
    8. mem write 0xFFFEC808 0x00A0 ;
    9. mem write 0xFFFEB048 0xAAAA ; stop the wahtchdog timer
    10. mem write 0xFFFEB048 0x5555
    11. ; setup DPLL for 96MHz freq
    12. mem or16 0xFFFECE08 0x4 ; enable ARM peripheral clock
    13. mem w16 0xFFFECE14 0x1 ; release OMAP CLKM reset
    14. mem w16 0xFFFECF00 0x2090 ; DPLL lock at 12MHz
    15. wait 150 ; wait until frequency is locked
    16. mem w16 0xFFFECE18 0x0 ; clocking mode : fully synchronous
    17. mem w16 0xFFFECE00 0x100A ; set the clock divisor for frequency 96MHz
    18. mem w16 0xFFFECF00 0x2413 ; set the DPLL for new frequency
    19. mem w16 0xFFFECE04 0x0 ;
    20. ; Setup TIPB (peripheral bus)
    21. mem w32 0xFFFEC900 0x0003FF2C ; set access width
    22. mem w16 0xFFFECA00 0xFF22 ; ARM private bus
    23. mem w16 0xFFFED300 0xFF22 ; ARM public bus
    24. ; configure EMIFS (slow external memory: flash)
    25. mem w32 0xFFFECC10 0x0000FFF3 ; EMIFS CS0 configuration
    26. mem w32 0xFFFECC14 0x0000AAA0 ; EMIFS CS1 configuration
    27. mem w32 0xFFFECC18 0x0000FFF3 ; EMIFS CS3 configuration
    28. mem w32 0xFFFECC1C 0x00003361 ; EMIFS CS3 configuration
    29. mem r32 0xFFFECC0C ; read EMIFS_CONFIG
    30. mem w8 0x00000000 0xFF ; reset flash to Read Array mode
    31. ; configure EMIFF (fast external memory: SDRAM-Mobile DDR)
    32. mem w32 0xFFFECC80 0x00000007 ; SDRAM type : mobile DDR SDRAM in HPHB mode
    33. mem w32 0xFFFECC20 0x0014E6FE ; SDRAM config
    34. mem w32 0xFFFECC84 0x00000000 ; DDR init : NOP
    35. mem w32 0xFFFECC84 0x00000001 ; DDR init : PRECHARGE
    36. mem w32 0xFFFECC84 0x00000002 ; DDR init : AUTOREFRESH
    37. mem w32 0xFFFECC84 0x00000002 ; DDR init : AUTOREFRESH
    38. mem w32 0xFFFECC70 0x00000033 ; DDR init : cas idle 3, page burst 8
    39. mem w32 0xFFFECC78 0x00000000 ; DDR init : self refresh all banks
    40. mem w32 0xFFFECCC0 0x00000006 ; DDR init : DDR DDL registers URD
    41. mem w32 0xFFFECCCC 0x00000006 ; DDR init : DDR DDL registers LRD
    42. mem w32 0xFFFECC64 0x00000006 ; DDR init : DDR DDL registers WRD
    Display All

    I tried to poke the mem w32 commands into J-Flash init steps:

    Source Code

    1. Halt
    2. Disable MMU
    3. Write32 FFFEC808 00F5 convert WD timer into GP timer
    4. Write32 FFFEC808 00A0
    5. Write32 FFFEB048 AAAA stop the wahtchdog timer
    6. Write32 FFFEB048 5555
    But this seems to have no effect. So i guess there is something missing. The commands unter "; reset ARM", maybe. I've read about the CPSR register which is set in front to disable CP15 and halt CPU? But don't know how to do this in J-Flash.



    The rest of the script i can't make any sense for J-Flash. Maybe their are also missing.



    Could someone please give me a hand on this?
  • Hello,

    Thank you for your inquiry.
    For generic scripting we suggest using a JLinkScript file which should give you all flexibility needed for complex init sequences.
    Watchdogs can be handled in two ways, either feed/reset it regularly or disable it. We recommend disabling it as this reduces complexity of your setup.
    The SPI Flash you mentioned is currently not supported officially to work out-of-the-box.
    To add support yourself the open flash loader interface can be used: wiki.segger.com/Adding_Support_for_New_Devices

    Please understand that we can't put much time into this inquiry as the OMAP5948 is not supported nor can we guarantee that third party init sequences will work at all.

    Best regards,
    Nino
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.
  • Hi Nino! Thanks for reply :)

    Yes, i will dig into JLinkScript. I found this tiny Wiki article wiki.segger.com/J-Link_script_files and the referred UM8001 handbook (btw: the link in the wiki downloads a file without suffix. I had to add '.pdf' myself to make it readable. Maybe one could fix this in Wiki).

    I aggree in disabling the Watchdog, and the Coprocessor (CP15) also. I guess in the moment J-Flash sends the "HALT" command to the CPU the Watchdog is not feed anymore and the following commands must disable it (which can only be done if the CPU is halted).

    I'm not shure if the flash is read by SPI. The Flash normally is in Array-Mode after reset. So it would be good to reset it before accessing it. After that each simple read will give a word on the dataports and increase the internal address counter. So it could be easily read, if there is no need for random access. Here i'm asking myself how to do it. Using basic JTAG to simulate the IO-Signals, or pushing a routine to the OMAPs RAM which uses OMAPs Flash-Interface (EMIF CS3) to read data and send it through a virtual channel through JTAG...

    Yes i know, i had to fight myself through this issue. I will, with a little help from you. If i get it to work, i'm willing to share if someone else runs into the same issue.

    I had some questions about the J-Flash Tool:
    When using "Disable MMU" in the init-steps, what will the tool send? Is it a pure JTAG-command or does manipulate some registers or uploads and executes some machinecode to do it?
    Also i wonder if downloading from Flash using J-Flash is done by pure JTAG bitbangig or by uploading and executing a programm into the CPUs RAM?

    Greetings,

    elektroll