[SOLVED] Renesas RZA1 enabling MMU affects SPI multi I/O registers

Allan R · May 25th 2018, 1:01pm

Hi,

We are currently using embOS v4.16 for ARM in an IAR EWARM environment, with the target being a Renesas RZA1H processor.

In the file rtosinit_R7S72100.c, in the call to __low_level_init() ,if I
enable the SPI Multi I/O bus controller, add the MMU entries to the translation
table and then call OS_ARM_MMU_Enable(_TranslationTable) I've found that the
registers for the SPI Multi I/O become unavailable.

I have attached 2 images to show the registers before and after enabling the MMU.

Thanks.

SEGGER - Til · May 25th 2018, 2:06pm

HI Allan,

I just did a quick test with a memory window and it looks ok.
The SPI multi I/O BUS space 1 is at physical address 0x18000000 and is mapped to the same virtual address 0x18000000.
The cache setting for this memory region is set to write through. The cache settings respectively the complete MMU table depends on your needs,
so you might want to use strongly ordered instead of write through which would be OS_ARM_CACHEMODE_NC_NB.

You are still in support, thus please don't hesitate to contact the embOS support directly by email.

Best regards,
Til

Allan R · May 30th 2018, 12:02pm

I have some example code from IAR using embOS that just flashes an LED.

I have found that the same thing happens with this code also. As soon as the call to
OS_ARM_MMU_Enable is executed the QSPI registers become unavailable.

I have attached the project for you to have a look at.

test2.zip

Thanks.

SEGGER - Til · May 30th 2018, 5:13pm

Thanks, we'll have a look into it.

Best regards,
Til

SEGGER - Til · May 30th 2018, 5:55pm

The IAR device definition file uses addresses at 0x3FEFA000:

C Source Code

;
; SPIBSC ch.0 (SPI with I/O Bus Controller channel 0)
;
; Name Zone Address Bytesize Displaybase Bitrange
; ---- ---- ------- -------- ----------- --------
sfr = "SPIBSC_CMNCR_0" , "Memory", 0x3FEFA000, 4, base=16
sfr = "SPIBSC_CMNCR_0.BSZ" , "Memory", 0x3FEFA000, 4, base=16, bitRange=0-1

Display All

This memory region is not mapped per default in our MMU table.
But you can easily add an according entry to it:
OS_ARM_MMU_AddTTEntries(_TranslationTable, OS_ARM_CACHEMODE_NC_NB, 0x3FE, 0x3FE, 0x001); // IO Area

Please note you have to reduce the previous section size accordingly:
OS_ARM_MMU_AddTTEntries(_TranslationTable, OS_ARM_CACHEMODE_ILLEGAL, 0x214, 0x214, 0x1EA); // Reserved area

In case of doubt I can also send you a complete project. But for that please contact our embOS support per email.
Please find the embOS support email address in the embOS manual in chapter "Support".

Does that solve your issue?

Best regards,
Til

Allan R · May 31st 2018, 3:41pm

That has done the trick.

Thanks for looking into this for me.

C Source Code

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