embos ERROR 166

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    • embos ERROR 166

      embOS for ARM version 4.30 with IAR workbench 7.8

      using STM32 family STM32F303VE controller

      Whenever I try to use OS interfaces its throwing os error 166(OS_ERR_CPU_STATE_ISR_ILLEGAL)


      Ex Interfaces;
      OS_EnterNestableInterrupt();
      OS_SignalEvent(JUPEvent, &TCB_JUPEvent);

      here is the code snipet of ISR handler

      void TIM3_IRQHandler(void)
      {
      OS_EnterNestableInterrupt();

      // Check for Timer Status register to know whether interrupt has occured
      if(((TIM3->SR & (DWORD)TIM_SR_UIF) == (DWORD)TIM_SR_UIF) != RESET)
      {
      // Check for Update Interrupt Enable bit
      if(((TIM3->DIER & (DWORD)TIM_DIER_UIE) == (DWORD)TIM_DIER_UIE) != RESET)
      {
      TIM3->SR &=~((DWORD)TIM_DIER_UIE) ;

      }
      }

      OS_LeaveNestableInterrupt();
      }


      please help..
    • Hi,

      are you using a valid embOS license or an embOS trial version?

      I am not sure if I understood your code snippet correctly.
      1. Where do you call OS_SignalEvent()?
      2. What is the last function before OS_Error() in your call stack?

      Basically this error message tells you that an embOS API was called from an invalid CPU state.
      That could e.g. happen with Cortex-M when your ISR routine used an invalid interrupt priority.
      I guess you are not using embOS ARM IAR but embOS Cortex-M IAR, correct?


      Best regards,
      Til
    • i am using valid embOS license version.

      i gave ex for OS_SignalEvent().......


      i am facing issue with both timer interrupt and os interfaces.

      i placed code for only timer interrupt....

      here is the full code

      //timer init function
      void Timer3Init(void)
      {

      // Enable Clock for TIMER3
      RCC->APB1ENR |= RCC_APB1ENR_TIM3EN;

      // Set the Edge-Aligned mode
      TIM3->CR1 &= ~(DWORD)(TIM_CR1_CMS);

      //Direction as Down counter
      TIM3->CR1 |= (DWORD)TIM_CR1_DIR;

      //set update request
      //This is to trigger interrupt only when there is underflow/overflow
      TIM3->CR1 |= (DWORD)TIM_CR1_URS;

      // Set the Timer clock frequency same as sampling clock for digital filters
      TIM3->CR1 &= ~((DWORD)TIM_CR1_CKD);

      // Set the Prescaler value as 71 so that tie timer peripheral runs at 1 MHz
      TIM3->CCMR1|= TIM_CCMR1_OC1PE;
      TIM3->PSC = 71;
      // Set the Auto reload value as 3000 for 3ms

      TIM3->ARR = (DWORD)10000;//((timerClkFreq / TIMER_CLK_DIVISON) * (DWORD)TIMER_THREEMILLISECOND);
      // Update Generation bit is SET so that the counter loaded Autoreload value automatically during downcounter
      TIM3->EGR |= (DWORD)TIM_EGR_UG;


      // Update interrupt enable
      TIM3->DIER |= (DWORD)TIM_DIER_UIE;

      // Update Generation bit is SET so that the counter loaded Autoreload value automatically during downcounter
      TIM3->EGR |= (DWORD)TIM_EGR_UG;


      // Set the Interrupt Priority and Sub-Priority
      I_STM_NVIC_SetPriority(TIM3_IRQn, 04, 00);

      // Enable the TIMER2 Interrupt
      I_STM_NVIC_EnableIRQ(TIM3_IRQn);
      // Enable the Counter
      TIM3->CR1 |= (DWORD)TIM_CR1_CEN;
      }

      ///timer irq function
      void TIM3_IRQHandler(void)

      {

      OS_EnterNestableInterrupt();



      // Check for Timer Status register to know whether interrupt has occured

      if(((TIM3->SR & (DWORD)TIM_SR_UIF) == (DWORD)TIM_SR_UIF) != RESET)

      {

      // Check for Update Interrupt Enable bit

      if(((TIM3->DIER & (DWORD)TIM_DIER_UIE) == (DWORD)TIM_DIER_UIE) != RESET)

      {

      TIM3->SR &=~((DWORD)TIM_DIER_UIE) ;



      }

      }



      OS_LeaveNestableInterrupt();

      }
    • // Set the Interrupt Priority and Sub-Priority
      I_STM_NVIC_SetPriority(TIM3_IRQn, 04, 00);


      Most likely that causes the problem but depends on how much interrupt priority bits are usable in your actual device.
      Could you please have a look in the CPU/Compiler specific embOS manual in chapter "Interrupts".
      Basically embOS splits the Cortex-M interrupt priorities in two parts: embOS interrupt priorities and zero latency interrupt priorities.
      embOS API can be called from interrupts with embOS interrupt priority only.

      Best regards,
      Til
    • Correct, the STM32F303 has 4 priority bits implemented.
      The actual priority register has 8 bits and the 4 lower bits are always zero.
      That means you can have the priorities 0x00, 0x10, 0x20...0xF0.
      Interrupt priorities below 0x80 arre zero latency interrupt priorities and anything else is an embOS interrupt priority.
      Please have in mind with Cortex-M lower value means higher priority, e.g. 0x00 ist the highest interrupt priority.

      Best regards,
      Til