[SOLVED] Structure of SWDIO pad of J-Link/J-Flash

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  • [SOLVED] Structure of SWDIO pad of J-Link/J-Flash

    Hi!
    Is Segger J-Link/J-Flash using a push-pull driver or open-drain on the SWDIO pad?
    Reason for my question is that the uController we are interfacing as an internal pull-down on SWDIO - which is against the recommendation in the ARM Debug Interface Architecture Specification, section 4.4.2 where a pull-up is required.
    When we put an external pull-up there is the problem of getting an intermediate voltage level (due to the internal pull-down) on SWDIO and cross-current. So, we want to get rid of the external pull-up and use only the pull-down. My understanding is, that the pull resistor is required to avoid SWDIO floating when no debugger is connected, which is also achieved by a pull-down. A pull-up is required in case the debugger is using an open-drain driver instead of push-pull.
    We already tried removing the external pull-up an Segger J-link still works, so I guess J-lInk uses a push-pull driver - just wanted to get the confirmation for this.
    Thanks,
    Christian
  • Hello Christian,

    Thank you for your inquiry.
    Correct, J-Link is configured push-pull.

    Best regards,
    Nino
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  • Hello Christian,

    Great to hear that your issue is resolved.
    We will consider this thread as solved now.

    Best regards,
    Nino
    Please read the forum rules before posting: Forum Rules

    Keep in mind, this is not a support forum. Its main purpose is user to user interaction.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support contact us per e-mail.
    The following contact form can be used for this: Contact Us