Hello,
I have a custom board with a ZYNQ 7020, RAM and a flash on it, which can be accessed and flashed problem-free through JTAG by the Xilinx software and the xilinx platform cable.
I tried using the Flasher ARM along with J-Flash and J-Link Commander to flash the board, using both the project generated by J-Flash and others I found on this forum, or using manual settings as opposed to autodetection, however this failed every time.
Sometimes it is not even able to connect, other times it says it can't find the CoreSight AP.
Attached you will find the settings and log files of two attempts that gave different results, along with the jflash project and the console output of when I tried J-Link commander.
This has been attempted on two PCs and the flasher works fine with other boards.

Thank you for your assistance.

Hi,

the hardware is a custom board, the memory to be programmed is a Micron N25Q256A11EF840E, connected via QSPI to the PS_MIO pins 1-6, just like in the evaluation boards. The memory can be programmed problem-free with Vivado Lab 2016.3 and the Xilinx Platform Cable USB II.

Thank you for your assistance.

Hi, I'm also posting the output of vivado lab correctly detecting the JTAG chain before programming the flash

# open_hw_target
INFO: [Labtoolstcl 44-466] Opening hw_target localhost:3121/xilinx_tcf/Xilinx/0000154b2a4e01
# create_hw_cfgmem -hw_device [current_hw_device] -mem_dev [lindex [get_cfgmem_parts {n25q256-qspi-x8-dual_parallel}] 0]
# set_property PROGRAM.ADDRESS_RANGE {entire_device} [current_hw_cfgmem]
# set_property PROGRAM.BLANK_CHECK 1 [current_hw_cfgmem]
# set_property PROGRAM.ERASE 1 [current_hw_cfgmem]
# set_property PROGRAM.CFG_PROGRAM 1 [current_hw_cfgmem]
# set_property PROGRAM.VERIFY 1 [current_hw_cfgmem]
# set_property PROGRAM.CHECKSUM 0 [current_hw_cfgmem]
# refresh_hw_device [current_hw_device]
INFO: [Labtools 27-1435] Device xc7z020 (JTAG device index = 1) is not programmed (DONE status = 0).
# set_property PROGRAM.FILES $programfile [current_hw_cfgmem]
# program_hw_cfgmem
Zynq cfgMem Intialize.
JTAG chain configuration
--------------------------------------------------
Device ID Code IR Length Part Name
1 0ba00477 4 arm_dap
2 03727093 6 xc7z020
--------------------------------------------------
Enabling extended memory access checks for Zynq.
Writes to reserved memory are not permitted and reads return 0.
To disable this feature, run "debugconfig -memory_access_check disable".
--------------------------------------------------
CortexA9 Processor Configuration
-------------------------------------
Version.............................0x00000003
User ID.............................0x00000000
No of PC Breakpoints................6
No of Addr/Data Watchpoints.........4
Processor Reset .... DONE
SF: Detected N25Q256A with page size 512 Bytes, erase size 8 KiB, total 64 MiB

Hi Nino,

the difference I've found is that on evaluation boards you can select the configuration mode settings with jumpers, while the board in my possession is built to boot in a specific mode without jumpers.

I have the following settings on the MIO[6:2] pins:
MIO2, 3, 4 pulled down
MIO5 pull up
MIO6 pull down

according to the zedboard hardware user guide, this corresponds to cascaded JTAG, Quad-SPI boot device and PLL used.

The JTAG circuit looks the same.

If you could verify with one of your evaluation boards whether setting the boot mode to this with the jumpers causes a similar issue, that would be great, as we don't have any evaluation boards.

Thank you.