[SOLVED] Options for tracing with limited pin availability on Cortex M

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  • [SOLVED] Options for tracing with limited pin availability on Cortex M

    OK, so I now have a J-trace Pro :thumbsup: and it is going to be used for full, real 4-pin ETM trace over ethernet on an upcoming project that is properly set up for it (micro with trace pins, and routed to a proper connector).

    But I would also like to figure out what is possible for older projects that were not or could not be set up for full trace. I know, these questions come up a lot given how many debug technologies there are now.

    One scenario is for an STM32F1 chip where SWD+SWO is available, but not the 5 dedicated ETM trace pins (small package, so pins not available). Is any kind of on-chip or on-probe buffered tracing possible? I believe statistical sampling over SWO would be possible, but I am trying to see if any in-order recording of steps is possible, so I could capture the last few hundred instructions before landing in an exception or code-initiated breakpoint.

    Another scenario is an STM32F4 micro inside an existing module, so only the SWD pins are available, not even SWO. Any options here?

  • Hello Andrew,

    Thank you for your inquiry.
    OK, so I now have a J-trace Pro :thumbsup: and it is going to be used for full, real 4-pin ETM trace over ethernet on an upcoming project that is properly set up for it

    Great to hear that you can use the J-Trace PRO in your project to the fullest.
    One scenario is for an STM32F1 chip where SWD+SWO is available, but not the 5 dedicated ETM trace pins (small package, so pins not available). Is any kind of on-chip or on-probe buffered tracing possible?

    Unfortunately in this case not as you would need either a ETB (embedded trace buffer) or MTB (ETB for Cortex-M0+) to do real tracing on internal buffers. Most (all?) STM32 devices do not have these.
    I believe statistical sampling over SWO would be possible, but I am trying to see if any in-order recording of steps is possible, so I could capture the last few hundred instructions before landing in an exception or code-initiated breakpoint.

    Yes, only statistical analysis over a periodic PC output would be possible in this case.
    Another scenario is an STM32F4 micro inside an existing module, so only the SWD pins are available, not even SWO. Any options here?

    In this case no "real" or statistical tracing is possible. But i might suggest looking into our free tool SystemView which is extracting as much information as possible form the target during run time.
    More information can be found here: segger.com/products/development-tools/about-systemview/
    Especially the post mortem functionality could be interesting to you: segger.com/products/developmen…hnology/post-mortem-mode/

    For future J-Trace PRO projects i suggest visiting the following pages:

    Tutorial: segger.com/products/debug-probes/j-trace/
    Setup/Troubleshooting: segger.com/products/debug-prob…hnology/setting-up-trace/
    List of tested devices with example projects: segger.com/products/debug-prob…echnology/tested-devices/

    Best regards,
    Nino
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