Jlink edu support for TI AM572x evaluation module

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  • Thanks a lot Niklas.

    The problem for me has been relating/translating this text (with no reference to connect, write or key in the text)

    ## Function : Do a send-only JTAG IR/DR scan.
    Parameter : The route to JTAG shift state is 'shortest transition'.
    Parameter : The JTAG shift state is 'shift-dr'.
    Parameter : The JTAG destination state is 'pause-dr'.
    Parameter : The bit length of the command is '8'.
    Parameter : The send data value is '0x00000089'.
    Parameter : The actual receive data is 'discarded'.

    to this

    _ICEPICK_CONNECT_WRITE_KEY = 0x89;


    Anyways, as of now, the current status is, I am still unable to connect to the target. I am getting
    Entering custom J-Link script file!
    ICEPick IDCODE: 0x00000000
    Cannot read DAP IDCODE. Expected 0xXXXXX02F, read: 0x00000000
    TotalIRLen = ?, IRPrint = 0x..000000000000000000000000
    cannot connect to target
    I think, I am unable to perform a TAP reset to make sure that icepick is the only device in the JTAG chain (to start with).

    The manual says (section: Initial Scan Chain Configuration), "The EMU0 and EMU1 pins should be pulled high at power-on-reset to configure the initial scan chain of the device to the TAP Router-only mode. In the TAP Router-only configuration, none of the secondary TAPs are selected. "

    But, the script seems to have writing JTAG sequence.
    // Perform a TAP reset to make sure that only the ICEPick is in the JTAG chain
    //
    JTAG_Write(0x1F, 0, 6);
    So, I am assuming, that if we write this sequence then both EMU0 and EMU1 are pulled high. So, how do I get the "tms" and "tdi" values to write the JTAG sequence?

    Also, could you please let me know how to get/confirm the following values.
    _ICEPICK_IR_IDCODE = 0x04;
    _DAP_IR_IDCODE = 0xE;
    Files
  • Hi,


    you are passing 0 to _ICEPick_AddTAP():

    C Source Code

    1. _ICEPick_AddTAP(_ICEPICK_SDTR0);


    But you need to pass 0x0F:
    The TAP number is 15


    Best regards,
    Niklas
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  • Thank you. I just changed it. The result is the same as can be seen in the attachment.

    For reference, I also changed the following two lines from AHB-AP to APB_AP (according to TRM, page 7871)

    JLINK_CORESIGHT_AddAP(1, CORESIGHT_APB_AP); // AHB-AP to System Bus
    JLINK_CORESIGHT_IndexAHBAPToUse = 1; // Cortex-M: AP-Index of AHB-AP to use for communication with core. Cortex-A/R: AP-Index of AHB-AP that can be used for SEGGER RTT
    Images
    • Screenshot_20170515_170835.png

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    The post was edited 3 times, last by solidrepellent ().

  • Hi,


    I am sorry, but this thread is way beyond "forum-support".
    We do not have the hardware here and this back and-forth (I suggest sth., you give it a try and report back) does not work out.

    I will ask in the next team meeting if we can order a board, but can not promise anything.

    I can also provide you with this "internal" script for the Ti AM335x, which is a Cortex-A8 (which is similar to a Cortex-A15).
    Maybe it helps.

    C Source Code

    1. /*********************************************************************
    2. * SEGGER MICROCONTROLLER GmbH & Co KG *
    3. * Solutions for real time microcontroller applications *
    4. **********************************************************************
    5. * *
    6. * (c) 2011-2017 SEGGER Microcontroller GmbH & Co KG *
    7. * *
    8. * www.segger.com Support: support@segger.com *
    9. * *
    10. **********************************************************************
    11. ----------------------------------------------------------------------
    12. Purpose : J-Link script file for TI AM335x device.
    13. - Initializes ICEPick
    14. - Handles reset
    15. ---------------------------END-OF-HEADER------------------------------
    16. */
    17. /*********************************************************************
    18. *
    19. * Static code
    20. *
    21. **********************************************************************
    22. */
    23. /*********************************************************************
    24. *
    25. * _StoreSelDP
    26. */
    27. void _StoreSelDP(void) {
    28. JTAG_StoreIR(0xA); // DPACC command
    29. JTAG_StoreClocks(1);
    30. }
    31. /*********************************************************************
    32. *
    33. * _StoreSelAP
    34. */
    35. void _StoreSelAP(void) {
    36. JTAG_StoreIR(0xB); // APACC command
    37. JTAG_StoreClocks(1);
    38. }
    39. /*********************************************************************
    40. *
    41. * _StoreTriggerReadAPDPReg
    42. *
    43. * Function description
    44. * Triggers a read of an AP or DP register. Depends on the previous command (DPACC / APACC)
    45. */
    46. int _StoreTriggerReadAPDPReg(unsigned int RegIndex) {
    47. U32 v;
    48. int BitPos;
    49. //
    50. // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
    51. //
    52. v = 1; // 1 indicates read access
    53. v |= (RegIndex << 1);
    54. JLINK_JTAG_StartDR();
    55. BitPos = JLINK_JTAG_WriteDRCont(v, 3);
    56. v = 0;
    57. JLINK_JTAG_WriteDREnd(v, 32);
    58. JTAG_StoreClocks(8);
    59. return BitPos;
    60. }
    61. /*********************************************************************
    62. *
    63. * _StoreWriteAPDPReg
    64. *
    65. * Function description
    66. * Writes an AP or DP register. Depends on the previous command (DPACC / APACC)
    67. */
    68. int _StoreWriteAPDPReg(unsigned int RegIndex, U32 Data) {
    69. U32 v;
    70. int BitPos;
    71. //
    72. // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
    73. //
    74. v = 0; // 0 indicates write access
    75. v |= (RegIndex << 1);
    76. JLINK_JTAG_StartDR();
    77. BitPos = JLINK_JTAG_WriteDRCont(v, 3);
    78. v = Data;
    79. JLINK_JTAG_WriteDREnd(v, 32);
    80. JTAG_StoreClocks(8);
    81. return BitPos;
    82. }
    83. /*********************************************************************
    84. *
    85. * _InitIcePick
    86. *
    87. * Function description
    88. * Configures the ICEPick so that the CPU core also becomes
    89. * visible in the JTAG chain.
    90. */
    91. void _InitIcePick(void) {
    92. int BitPos;
    93. int v;
    94. int ICEPickIdCode;
    95. int DPIdCode;
    96. int Speed;
    97. Report("J-Link script: Init ICEPick");
    98. Speed = JTAG_Speed;
    99. JTAG_Speed = 100;
    100. JTAG_Reset(); // Perform TAP reset and J-Link JTAG auto-detection
    101. if (JTAG_TotalIRLen != 6) {
    102. Report("Can not find ICE-Pick (IRLen mismatch)");
    103. }
    104. JTAG_DRPre = 0;
    105. JTAG_DRPost = 0;
    106. JTAG_IRPre = 0;
    107. JTAG_IRPost = 0;
    108. JTAG_IRLen = 6;
    109. //
    110. // Check IDCODE of ICEPick (do not confuse with ICEPICKCODE or IDCODE of JTAG-DP)
    111. //
    112. JTAG_StoreIR(4); // IDCODE instruction for ICEPick device
    113. BitPos = JTAG_StoreDR(0x00000000, 32);
    114. ICEPickIdCode = JTAG_GetU32(BitPos);
    115. if ((ICEPickIdCode & 0x0F000FFF) != 0x0B00002F) { // highest nibble holds version information, so it can not be used for verification.
    116. MessageBox1("Can not find ICE-Pick (IDCODE mismatch). Expected 0x0B00002F, found: ", ICEPickIdCode);
    117. return 1;
    118. }
    119. //
    120. // Put the core in the JTAG chain
    121. //
    122. JTAG_StoreIR(7); // CONNECT
    123. JTAG_StoreDR(0x89, 8); // Put ICEPick module into connected state by writing the connect key. Bit 7 == 1 indicates write
    124. JTAG_StoreIR(2); // ROUTER (Accessing the mapped registers)
    125. v = 0
    126. | (0xAC << 24) // Write SDTAP12
    127. | (1 << 13) // Debug Connect
    128. | (1 << 8) // TAP select
    129. | (1 << 3) // Force active
    130. ;
    131. JTAG_StoreDR(v, 32); // Write SDTAP12
    132. JTAG_StoreDR(0xE0002008, 32);
    133. JTAG_StoreIR(0x3F); // BYPASS
    134. JTAG_WriteClocks(10);
    135. //
    136. // Configure JTAG chain, so J-Link knows to which device it has to "talk" to.
    137. // CPU core is in scan chain now, so we have to re-configure the JTAG chain settings.
    138. // The CPU core is device 0 (closest to TDO).
    139. //
    140. JTAG_IRPre=0;
    141. JTAG_DRPre=0;
    142. JTAG_IRPost=6;
    143. JTAG_DRPost=1;
    144. JTAG_IRLen=4;
    145. CPU=CORTEX_A8;
    146. JTAG_AllowTAPReset=0;
    147. //
    148. // Check core ID
    149. //
    150. JTAG_StoreIR(0xE); // Read JTAG-DP IDCODE register
    151. v = 0;
    152. BitPos = JTAG_StoreDR(v, 32); // Get ID
    153. DPIdCode = JTAG_GetU32(BitPos);
    154. if ((DPIdCode & 0x00000FFF) != 0x00000477) {
    155. Report("Can not find Cortex-A8 (IDCODE mismatch)");
    156. return 1;
    157. }
    158. //
    159. // Set JTAG Ids for all devices in the JTAG chain
    160. //
    161. JTAG_SetDeviceId(0, DPIdCode);
    162. JTAG_SetDeviceId(1, ICEPickIdCode);
    163. //
    164. // Set AP info for all APs in the device
    165. //
    166. CORESIGHT_AddAP(0, CORESIGHT_AHB_AP);
    167. CORESIGHT_AddAP(1, CORESIGHT_APB_AP);
    168. CORESIGHT_AddAP(2, CORESIGHT_JTAG_AP);
    169. CORESIGHT_CoreBaseAddr = 0x80001000;
    170. JTAG_WriteClocks(1); // Make sure that JTAG buffers are empty
    171. JTAG_Speed = Speed;
    172. return 0;
    173. }
    174. /*********************************************************************
    175. *
    176. * Public code, functions which are called by the DLL
    177. *
    178. **********************************************************************
    179. */
    180. /*********************************************************************
    181. *
    182. * ResetTarget
    183. */
    184. void ResetTarget(void) {
    185. int Speed;
    186. int BitPos;
    187. int Ctrl;
    188. int bcr0;
    189. int bcr1;
    190. int bvr0;
    191. int bvr1;
    192. int AddrBVR;
    193. int AddrBCR;
    194. int AddrDSCR;
    195. int AddrDRCR;
    196. U32 v;
    197. Report("J-Link script: Reset");
    198. Speed = JTAG_Speed;
    199. JTAG_Speed = 100;
    200. AddrBVR = 0x80001000 + (0x40 << 2);
    201. AddrBCR = 0x80001000 + (0x50 << 2);
    202. AddrDSCR = 0x80001000 + (0x22 << 2);
    203. AddrDRCR = 0x80001000 + (0x24 << 2);
    204. Ctrl = 0
    205. | (2 << 0) // AP-access size. Fixed to 2: 32-bit
    206. | (1 << 4) // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
    207. | (1 << 31) // Enable software access to the Debug APB bus.
    208. ;
    209. _StoreSelDP();
    210. _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4)); // Select AP[1] (APB-AP), bank 0
    211. _StoreSelAP();
    212. _StoreWriteAPDPReg(0, Ctrl);
    213. //
    214. // Remember settings for BP unit 0 and 1
    215. //
    216. _StoreWriteAPDPReg(1, AddrBVR);
    217. _StoreTriggerReadAPDPReg(3);
    218. BitPos = _StoreTriggerReadAPDPReg(3);
    219. bvr0 = JTAG_GetU32(BitPos + 3);
    220. BitPos = _StoreTriggerReadAPDPReg(3);
    221. bvr1 = JTAG_GetU32(BitPos + 3);
    222. _StoreWriteAPDPReg(1, AddrBCR);
    223. _StoreTriggerReadAPDPReg(3);
    224. BitPos = _StoreTriggerReadAPDPReg(3);
    225. bcr0 = JTAG_GetU32(BitPos + 3);
    226. BitPos = _StoreTriggerReadAPDPReg(3);
    227. bcr1 = JTAG_GetU32(BitPos + 3);
    228. //
    229. // Disable breakpoints on BP unit 0 and 1
    230. //
    231. _StoreWriteAPDPReg(1, AddrBCR);
    232. _StoreWriteAPDPReg(3, 0x00000000);
    233. _StoreWriteAPDPReg(3, 0x00000000);
    234. //
    235. // Set breakpoints
    236. // Break at 0x000240C0 which is a dead loop in the installer that is called if booting from NOR flash was selected but failed since NOR flash is empty
    237. // Break as soon as the CPU jumps to an address higher than 0x3FFFF. 0x0 - 0x20FFF is occupied by the bootloader at startup. RAM is beyond 0x3FFFF. When booting from NOR flash from CS0, the bootloader maps it to 0x08000000 and jumps to it.
    238. //
    239. _StoreWriteAPDPReg(1, AddrBVR);
    240. _StoreWriteAPDPReg(3, 0x00000000);
    241. _StoreWriteAPDPReg(3, 0x000200C0);
    242. //
    243. // Enable the breakpoints
    244. //
    245. _StoreWriteAPDPReg(1, AddrBCR);
    246. _StoreWriteAPDPReg(3, 7 | (0xF << 5) | (4 << 20) | (18 << 24));
    247. _StoreWriteAPDPReg(3, 7 | (0xF << 5) | (0 << 20));
    248. JTAG_WriteClocks(1); // Make sure that JTAG buffers are empty and breakpoint is set
    249. //
    250. // Setup JTAG config to "talk" to the ICEPick, so we can use the JTAG API functions
    251. //
    252. JTAG_DRPre = 1;
    253. JTAG_DRPost = 0;
    254. JTAG_IRPre = 4;
    255. JTAG_IRPost = 0;
    256. JTAG_IRLen = 6;
    257. //
    258. // Perform reset via ICEPick system control register, by setting the SysReset bit
    259. //
    260. JTAG_StoreIR(2); // Cmd: ROUTER
    261. v = 0x01000000; // Read SYS_CNTL
    262. JTAG_StoreDR(v, 32); // Send read register command
    263. BitPos = JTAG_StoreDR(v, 32); // Shift out register content
    264. v = JTAG_GetU32(BitPos);
    265. v &= 0x00FFFFFF;
    266. v |= 0x81000001; // Write SYS_CNTL and set SysReset bit
    267. JTAG_StoreDR(v, 32);
    268. JTAG_WriteClocks(10); // The reset needs some time to get active
    269. //
    270. // Setup JTAG config to "talk" to the Cortex-R4 again
    271. //
    272. JTAG_DRPre = 0;
    273. JTAG_DRPost = 1;
    274. JTAG_IRPre = 0;
    275. JTAG_IRPost = 6;
    276. JTAG_IRLen = 4;
    277. SYS_Sleep(200); // If device boots from NAND, make sure it has enough time to copy the second level bootloader and jump to it
    278. //
    279. // Check if CPU is halted. If not, halt it.
    280. // Select & setup APB-AP
    281. //
    282. _StoreSelDP();
    283. _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4)); // Select AP[1], bank 0
    284. _StoreSelAP();
    285. _StoreWriteAPDPReg(0, Ctrl);
    286. //
    287. // Read DSCR to check if CPU is halted
    288. //
    289. _StoreWriteAPDPReg(1, AddrDSCR);
    290. _StoreTriggerReadAPDPReg(3);
    291. _StoreSelDP();
    292. BitPos = _StoreTriggerReadAPDPReg(3);
    293. v = JTAG_GetU32(BitPos + 3);
    294. _StoreSelAP();
    295. if ((v & 1) == 0) {
    296. //
    297. // If CPU did not halt after reset, halt it
    298. //
    299. Report("J-Link script: Core did not halt after reset. Halting core...");
    300. v |= (1 << 14);
    301. _StoreWriteAPDPReg(1, AddrDSCR); // Enable debug halt mode by writing the DSCR
    302. _StoreWriteAPDPReg(3, v);
    303. _StoreWriteAPDPReg(1, AddrDRCR); // Write DRCR to halt CPU
    304. _StoreWriteAPDPReg(3, 1);
    305. JTAG_WriteClocks(1);
    306. }
    307. //
    308. // Restore BP settings
    309. //
    310. _StoreWriteAPDPReg(1, AddrBVR);
    311. _StoreWriteAPDPReg(3, bvr0);
    312. _StoreWriteAPDPReg(3, bvr1);
    313. _StoreWriteAPDPReg(1, AddrBCR);
    314. _StoreWriteAPDPReg(3, bcr0);
    315. _StoreWriteAPDPReg(3, bcr1);
    316. _StoreSelDP();
    317. JTAG_WriteClocks(1);
    318. JTAG_Speed = Speed;
    319. }
    320. /*********************************************************************
    321. *
    322. * InitEMU
    323. */
    324. void InitEMU(void) {
    325. EMU_ETB_IsPresent = 0;
    326. }
    327. /*********************************************************************
    328. *
    329. * InitTarget
    330. */
    331. void InitTarget(void) {
    332. Report("TI AM335x (Cortex-A8 core) J-Link script");
    333. //
    334. // By performing a TRST reset, we make sure that only the ICEPick module is in the scan chain
    335. //
    336. EMU_JTAG_DisableHWTransmissions = 1; // We are not allowed to use the HW-units of the J-Link to transmit JTAG data
    337. JTAG_TRSTPin = 0;
    338. SYS_Sleep(50);
    339. JTAG_TRSTPin = 1;
    340. SYS_Sleep(50);
    341. JTAG_Write(0x1F, 0, 6);
    342. _InitIcePick();
    343. }
    Display All


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/

    Or you can contact us via e-mail.