[SOLVED] Mulitcore debugging with NXP iMX6

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  • [SOLVED] Mulitcore debugging with NXP iMX6

    Hi,
    I have a -link Ultra+ connected to an NXP iMX6 (on a QWKS-SCMIMX6 development board) I need to be able to connect to and debug each of the ARM A9 cores in the SOC separately. I have seen mention of using separate GDB servers one of each core in order to do this, but in my case I am not using GDB. My development environment is Rowley CrossStudio which uses the JLinkARM.dll to interface to the j-link.

    If I set the following in the Rowley target connect script,


    TargetInterface.setDebugInterfaceProperty("set_adiv5_APB_ap_num", 1)
    TargetInterface.setDebugInterfaceProperty("component_base", 0x82150000 )

    I am able to connect to core 0, load and debug code just fine.

    I tried changing the 'component_base' to 0x821520000 (for Core 1) but then the connect fails as follows,


    Connecting ‘SEGGER J-Link’
    Connecting to target using JTAG
    Loaded C:/Program Files (x86)/SEGGER/JLink_V610f/JLinkARM.dll
    Firmware Version: J-Link Ultra V4 compiled Sep 1 2016 18:31:22
    DLL Version: 6.10f
    Hardware Version: V4.00
    Target Voltage: 3.135
    Executing connect script
    Loading target script file ARM_Target.js
    Executing script TargetInterface.setDebugInterfaceProperty("set_adiv5_APB_ap_num", 1)
    TargetInterface.setDebugInterfaceProperty("component_base", 0x82152000 )
    Device "MCIMX6Q4" selected.
    TotalIRLen = 13, IRPrint = 0x0101
    ARM AP[0]: 0x44770001, AHB-AP
    ARM AP[1]: 0x24770002, APB-AP
    ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-003BB907 ETB
    ROMTbl 0 [1]: 00002003, CID: B105900D, PID:04-002BB906 ECT / CTI
    ROMTbl 0 [2]: 00003003, CID: B105900D, PID:04-004BB912 TPIU
    ROMTbl 0 [3]: 00004003, CID: B105900D, PID:04-001BB908 CSTF
    ROMTbl 0 [4]: 0000F003, CID: B105100D, PID:04-000BB4A9 ROM Table
    ROMTbl 1 [0]: 00001003, CID: B105900D, PID:04-000BBC09 Cortex-A9
    Found Cortex-A9 r2p10
    6 code breakpoints, 4 data breakpoints
    Debug architecture ARMv7.0
    Data endian: little
    Main ID register: 0x412FC09A
    I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    System control register:
    Instruction endian: little
    Level-1 instruction cache enabled
    Level-1 data cache disabled
    MMU disabled
    Branch prediction disabled
    Identifying
    ROM Table ID 0x18181818 Base Address 0x82152000 Peripheral ID 0x1818181818 4KB Count = 2 JEP 106 code = 0x8 0x1 RevAnd 0x1 Customer Modified 0x8 Rev 1 Part Number 0x818 Device ID 0x38 Device Type 0x38
    ROM Table 0x82152000
    Skipping ROM Table Entry 0x006fdb6c
    Skipping ROM Table Entry 0x006fdb6c
    .
    . (the "Skipping ROM Table Entry" message repeats many times...)
    .
    Detected core type doesn't agree with debug interface type project property


    Should this work?

    Neil

  • Can I assume due to the lack of response on my question that it is not possible to multicore debug using the JLinkARM.dll interface?

    I have also been in contact with Rowley and they do not know how to configure.

    Neil

  • Hi Neil,

    sorry for the delay in response.

    General note: In most cases, if a Logfile does not fit in a forum post, it is helpful to additionally provide a unabridged version as an attachment to the post.

    Could you please tell us which device is used on this eval board (nxp.com/products/microcontroll…_SERIES?tid=vanIMX6SERIES for reference).
    "MCIMX6Q4" is incorrect here, as this is a different device which features a Cortex-M4 and a Cortex-A9 core.

    As a first step, could you please give J-Link Commander (J-Link Exe) a try?
    -> Please check the reference manual of the device in order to find out if the 2nd A9 is running per default or if it is necessary to activate the 2nd A9 with the first A9
    -> Open J-Link Commander
    -> Connect to the first A9 ( Specify device as Cortex-A9 )
    -> Execute all steps necessary in order to activate the 2nd A9 (if it is not running per default)
    -> Quit J-Link Commander and open a new session
    -> Connect to the 2nd A9

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Niklas,

    Thanks for your reply.

    The i.MX6 device in the SoC I am using is this one, nxp.com/products/microcontroll…x-a9-core:i.MX6Q#overview. However it is limited to a clock speed of 800MHz. It has 4 Cortex A9 cores, and as far as I can tell from the device manuals they are operating as per default.

    If I use J-Link.exe I see this,


    SEGGER J-Link Commander V6.10f (Compiled Oct 17 2016 17:41:50)
    DLL version V6.10f, compiled Oct 17 2016 17:41:18

    Connecting to J-Link via USB...O.K.
    Firmware: J-Link Ultra V4 compiled Sep 1 2016 18:31:22
    Hardware version: V4.00
    S/N: 504401606
    License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    VTref = 3.130V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: MCIMX6Q4
    Type '?' for selection dialog
    Device>?

    When I type the ? I see the 'Target device settings' window. If I then select Cortex-A9 from the 'Core' drop down list, around 25 different Freescale/NXP MCIMX6xy variants are shown, however none of them has more than 1 core as shown under 'NumCores' column. Can you tell me which one variant I need to use for multicore debuging? If I select MCIMX6Q4 I can connect to core 0.

    In order to remove CrossWorks from this issue I moved my project over to an evaluation version of IAR Workbench and also cannot configure multicore debugging (In IAR there
    is a ‘Multicore’ tab in the Debugger options for the project which looked
    hopeful, but unfortunately all the controls on the page are greyed out).


    Neil

  • Hi,

    the device is not in the list of supported devices, therefore you need to type in "Cortex-A9" when you are asked for the device name.
    Can you connect to the other cores by specifying the respective IRPre and DRPre values in J-Link Commander?

    If not, does the reference manual of the device say sth. about how to enable the other cores?

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Niklas,

    I am struggling to find information about the IRPre and DRPrn values for the other cores....and also what state these cores are in at power-up.

    This is the output I see if I connect to the device and specify 'Cortex-A9'


    SEGGER J-Link Commander V6.10f (Compiled Oct 17 2016 17:41:50)
    DLL version V6.10f, compiled Oct 17 2016 17:41:18

    Connecting to J-Link via USB...O.K.
    Firmware: J-Link Ultra V4 compiled Sep 1 2016 18:31:22
    Hardware version: V4.00
    S/N: 504401606
    License(s): RDI, FlashBP, FlashDL, JFlash, GDB
    VTref = 3.137V


    Type "connect" to establish a target connection, '?' for help
    J-Link>connect
    Please specify device / core. <Default>: CORTEX-A9
    Type '?' for selection dialog
    Device>cortex-a9
    Please specify target interface:
    J) JTAG (Default)
    S) SWD
    TIF>
    Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    JTAGConf>
    Specify target interface speed [kHz]. <Default>: 4000 kHz
    Speed>
    Device "CORTEX-A9" selected.


    TotalIRLen = 13, IRPrint = 0x0101

    **************************
    WARNING: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)

    **************************

    ARM AP[0]: 0x44770001, AHB-AP
    ARM AP[1]: 0x24770002, APB-AP
    ROMTbl 0 [0]: 00001003, CID: B105900D, PID:04-003BB907 ETB
    ROMTbl 0 [1]: 00002003, CID: B105900D, PID:04-002BB906 ECT / CTI
    ROMTbl 0 [2]: 00003003, CID: B105900D, PID:04-004BB912 TPIU
    ROMTbl 0 [3]: 00004003, CID: B105900D, PID:04-001BB908 CSTF
    ROMTbl 0 [4]: 0000F003, CID: B105100D, PID:04-000BB4A9 ROM Table
    ROMTbl 1 [0]: 00001003, CID: B105900D, PID:04-000BBC09 Cortex-A9
    Found Cortex-A9 r2p10
    6 code breakpoints, 4 data breakpoints
    Debug architecture ARMv7.0
    Data endian: little
    Main ID register: 0x412FC09A
    I-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    D-Cache L1: 32 KB, 256 Sets, 32 Bytes/Line, 4-Way
    System control register:
    Instruction endian: little
    Level-1 instruction cache enabled
    Level-1 data cache disabled
    MMU disabled
    Branch prediction disabled
    Found 3 JTAG devices, Total IRLen = 13:
    #0 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
    #1 Id: 0x00000001
    #2 Id: 0x2191C01D
    Cortex-A9 identified.
    J-Link>

    Neil

  • Hi Neil,

    turns out that the i.MX6DQ does not have the devices in a JTAG-chain, but instead the different cores are available via the ABP-AP.
    Sorry for any inconvenience caused, but as I mentioned, we do not support this device yet and also do not have the hardware here.

    I prepared a wiki article which explains how to connect to the different cores and provides the necessary J-Link script files, so that you do not need to write it by yourself.
    wiki.segger.com/IMX6DQ

    You still need the refer to the reference manual on how to enable / get Cores 1-3 out of reset.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Niklas,

    Thanks for the information. It is strange you don't support this device as I definitely read somewhere in the NXP documentation that the SEGGER j-link was the recommended j-tag device....

    I have tried one of your scripts from IAR Workbench and I still can't connect to one of the other Cores. NXP documentation implies that when core 0 is in the boot ROM, all the other cores will be executing the WFI (Wait for Interrupt) instruction. Should I be able to connect in that state or do I need them actually executing code? This is what happens when I try and connect to core 1 having added your script to the j-link control panel settings.


    Wed Jan 11, 2017 17:59:28: IAR Embedded Workbench 7.80.3 (armproc.dll)
    Wed Jan 11, 2017 17:59:28: Device "MCIMX6Q4" selected.
    Wed Jan 11, 2017 17:59:28: JLINK command: ProjectFile = D:\Open Stack\Checkouts\Piciorgros_SVN\NXP_IMX6_IAR\Bootloader\Make\settings\NXP_Bootloader_Debug.jlink, return = 0
    Wed Jan 11, 2017 17:59:28: Device "MCIMX6Q4" selected.
    Wed Jan 11, 2017 17:59:28: DLL version: V6.12
    Wed Jan 11, 2017 17:59:28: Firmware: J-Link Ultra V4 compiled Sep 1 2016 18:31:22
    Wed Jan 11, 2017 17:59:28: JTAG speed is fixed to: 4000 kHz
    Wed Jan 11, 2017 17:59:28: Initial reset was performed
    Wed Jan 11, 2017 17:59:28: TotalIRLen = 13, IRPrint = 0x0101
    Wed Jan 11, 2017 17:59:28: Warning: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
    Wed Jan 11, 2017 17:59:28: CoreSight AP[0]: 0x04770001, AHB-AP
    Wed Jan 11, 2017 17:59:28: CoreSight AP[1]: 0x04770002, APB-AP
    Wed Jan 11, 2017 17:59:28: Found Cortex-A9 r0p2
    Wed Jan 11, 2017 17:59:28: 2 code breakpoints, 3 data breakpoints
    Wed Jan 11, 2017 17:59:28: Debug architecture ARMv7.0
    Wed Jan 11, 2017 17:59:28: TotalIRLen = 13, IRPrint = 0x0101
    Wed Jan 11, 2017 17:59:28: Warning: At least one of the connected devices is not JTAG compliant (IEEE Std 1149.1, 7.1.1.d, IR-cells). (NumDevices = 3, NumBitsSet = 2)
    Wed Jan 11, 2017 17:59:37: Fatal error: Cortex-A/R (connect): Could not unlock debug registers Session aborted!
    Wed Jan 11, 2017 17:59:37: IAR Embedded Workbench 7.80.3 (armproc.dll)

    Incidentally how do you remove this script once added to the settings in the control panel? I can browse and select a file to add, but there doesn't seem to be any way to set the script file box back to empty!

    Regards,
    Neil

  • Hi Neil,


    sorry for the delay in response.
    I updated the wiki, it now also contains a J-Link Commander file which can be used to activate the other cores of the device.
    wiki.segger.com/IMX6DQ

    Procedure is as follows:
    1. Open J-Link Commander with the following command line parameters: -commanderscript PATHTOFILE/iMX6DQ_Activate4Cores.jlink -jtagconf -1,-1
    2. Open a session of IAR EWARM for each core you want to debug.
    3. Add the respective .JLinkScript to each IAR EWARM project (Except Core 0, which does not need one)
    4. Start the debug sessions.


    Incidentally how do you remove this script once added to the settings in the control panel? I can browse and select a file to add, but there doesn't seem to be any way to set the script file box back to empty!

    You do not need to do this for this use case (see above). You can point to an empty file if necessary. I will take a look if we can add an "clear script file" option.

    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.

  • Hi Neil,



    thanks for the feedback!
    Good to hear that you are finally up and running :)


    Best regards,
    Niklas
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
    Or you can contact us via e-mail.