JTAG Debugging of TI DRA74x [****** Error: CPU is not halted]

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  • JTAG Debugging of TI DRA74x [****** Error: CPU is not halted]


    I am working on a custom board that uses the TI DRA74x SoC.
    I have configured the scan chain to expose the A15 and IPU0 M4 cores; however I can only successfully debug the A15.


    I have attached the working A15 JlinkScript. Altering the last line to SetCore(2) exposes the M4.
    The M4 is being correctly initialised by the A15 and is executing code when I try to connect and I can use the "mem" command in JLinkExe.
    For some reason, JLink thinks that the core is not halted, yet the code is paused (display animation output halts).
    Is there a step that I am missing to tell JLink about the M4 in order to debug it correctly?
    Any help is much appreciated.

    I get the following error when using GDB:

    Source Code

    1. $ JLinkGDBServer -ScriptFile dra74x.JLinkScript -device CORTEX-M4 -speed 8000
    2. SEGGER J-Link GDB Server V6.12a Command Line Version
    3. JLinkARM.dll V6.12a (DLL compiled Dec 2 2016 17:00:59)
    4. -----GDB Server start settings-----
    5. GDBInit file: none
    6. GDB Server Listening port: 2331
    7. SWO raw output listening port: 2332
    8. Terminal I/O port: 2333
    9. Accept remote connection: yes
    10. Generate logfile: off
    11. Verify download: off
    12. Init regs on start: off
    13. Silent mode: off
    14. Single run mode: off
    15. Target connection timeout: 0 ms
    16. ------J-Link related settings------
    17. J-Link Host interface: USB
    18. J-Link script: dra74x.JLinkScript
    19. J-Link settings file: none
    20. ------Target related settings------
    21. Target device: CORTEX-M4
    22. Target interface: JTAG
    23. Target interface speed: 8000kHz
    24. Target endian: little
    25. Connecting to J-Link...
    26. J-Link is connected.
    27. Firmware: J-Link V9 compiled Dec 2 2016 15:35:20
    28. Hardware: V9.30
    29. S/N: 59305236
    30. Feature(s): GDB
    31. Checking target voltage...
    32. Target voltage: 3.38 V
    33. Listening on TCP/IP port 2331
    34. Connecting to target...
    35. J-Link found 4 JTAG devices, Total IRLen = 18
    36. JTAG ID: 0x4BA00477 (Cortex-M4)
    37. ERROR: Could not connect to target.
    38. Target connection failed. GDBServer will be closed...Restoring target state and closing J-Link connection...
    39. Shutting down...
    40. Could not connect to target.
    41. Please check power, connection and settings.
    Display All

    The debug output from JLinkExe:

    Source Code

    1. $ JLinkExe -JLinkScriptFile dra74x.JLinkScript -device CORTEX-M4 -speed 8000 -if jtag
    2. SEGGER J-Link Commander V6.12a (Compiled Dec 2 2016 17:01:07)
    3. DLL version V6.12a, compiled Dec 2 2016 17:00:59
    4. Connecting to J-Link via USB...O.K.
    5. Firmware: J-Link V9 compiled Dec 2 2016 15:35:20
    6. Hardware version: V9.30
    7. S/N: 59305236
    8. License(s): GDB
    9. VTref = 3.380V
    10. Type "connect" to establish a target connection, '?' for help
    11. J-Link>con
    12. Device position in JTAG chain (IRPre,DRPre) <Default>: -1,-1 => Auto-detect
    13. JTAGConf>
    14. Device "CORTEX-M4" selected.
    15. DRA74x J-Link script
    16. Could not measure total IR len. TDO is constant high.
    17. Selected M4 Core #0
    18. TotalIRLen = 18, IRPrint = 0x001111
    19. AP-IDR: 0x24770011, Type: AHB-AP
    20. Start searching for Cortex-M ROM table with ROMTable[0] @ 0xE00FF000.
    21. ROMTable[-317433376]: Cortex-M ROM table found.
    22. Found Cortex-M4 r0p1, Little endian.
    23. FPUnit: 6 code (BP) slots and 2 literal slots
    24. CoreSight components:
    25. ROMTbl 0 @ E00FF000
    26. ROMTbl 0 [0]: FFF0F000, CID: B105E00D, PID: 000BB000 SCS
    27. ROMTbl 0 [1]: FFF02000, CID: B105E00D, PID: 003BB002 DWT
    28. ROMTbl 0 [2]: FFF03000, CID: B105E00D, PID: 002BB003 FPB
    29. ROMTbl 0 [3]: FFF01000, CID: 00000000, PID: 00000000 ???
    30. ROMTbl 0 [4]: FFF41000, CID: 00000000, PID: 00000000 ???
    31. ROMTbl 0 [6]: FFF43000, CID: 00000000, PID: 00000000 ???
    32. Found 4 JTAG devices, Total IRLen = 18:
    33. #0 Id: 0x3BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
    34. #1 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
    35. #2 Id: 0x4BA00477, IRLen: 04, IRPrint: 0x1, CoreSight JTAG-DP (ARM)
    36. #3 Id: 0x0B99002F, IRLen: 06, IRPrint: 0x1, TI ICEPick
    37. Cortex-M4 identified.
    38. J-Link>mem 0x48975500 0x10
    39. 48975500 = 00 00 00 00 0A A1 40 00 D0 02 80 07 00 00 00 00
    40. J-Link>h
    41. **************************
    42. WARNING: CPU could not be halted
    43. **************************
    44. J-Link>mem 0x48975500 0x10
    45. Could not read memory.
    46. J-Link>
    Display All

    The post was edited 1 time, last by richt123 ().

  • Hi,

    From the script and from the output of J-Link Commander, it seems that basic identification of the M4 works fine.
    However, when the read request is issued, it seems that the connection to the whole AHB-AP is lost as even reading memory fails after the failing halt request has been done.

    Is the M4 in your case actually executing code or is it possible that the M4 is powered etc. but kept in reset?
    From what I see in the output below, this is a typical effect of having a secondary core etc . powered but kept in reset (some debug registers are accessible via the AHB-AP, but actual debug requests to the core result in erroneous behavior)

    Is it possible that the M4 is entering some kind of low power mode between the execution of code, that may cause this problem?
    From what I can say, M4 support on J-Link is working 100% fine and in 99.9% of the cases, such problems on multi-core systems are configuration issues (reset active, secondary core reset by accident, secondary core not powered, ...)

    Best regards
  • Hi Alex,

    The M4 is executing code. It is doing a simple animation on the HDMI display output.
    When I initiate the connection, the animation stops implying that the M4 core is either halted or reset by the J-Link.
    The rest of the system is not reset, as the display contents remain valid.

    Kind regards,