[ABANDONED] JTAG chain - CPU-TAP not found

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  • [ABANDONED] JTAG chain - CPU-TAP not found

    I have a JTAG-chain consisting of a VF6XX_A5 MCU and a Igloo nano FPGA. I am using J_Link PlUS, and I know that I can not expect to program the FPGA out of the box, but shouldn't I be able to program the MCU, even though there are a FPGA on the chain?


    The chain is configured as following:

    TDI --> VF6XX_A5 (IRlen 4) --> Igloo nano (IRlen 8) -->
    TDO <--------------------------------------------------------


    I am using J_link Commander to try to connect to the MCU.
    The setting I am using is
    Device: VF6XX_A5,
    TIF: JTAG,
    JTAGConf: -1,-1 (I have tried 0,0 which should be the correct according my setup)
    Speed 4000 KHz

    But the respons i get is:
    Device "VF6XX_A5" selected.


    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D

    ****** Error: CPU-TAP not found in JTAG chain

    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D
    TotalIRLen = 12, IRPrint = 0x019D

    ****** Error: CPU-TAP not found in JTAG chain

    Can not connect to target.

    Can anyone help me? I am out if ideas..
  • Hi,

    if you do not connect to the target but use the JTAG Commands provided by J-Link Commander like e.g. described in this post,
    do you get the excepted response (IDCODE) of the A5? If not, does it work with SEGGER JTAGLoad?


    Best regards,
    Niklas
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  • Hi Nikhilesh and Niklas

    Sorry my very delayed respons on this. We decided at that it wasn't necessary to connect to the devices in a chain anymore, and so we didn't need to spend time on this. But now this up as a topic again.

    Do you have any ide on how to set the vybrid in boundary scan mode. What I found in the referance manual is this:


    JTAG-toJTAG to cJTAG change sequence
    • Reset the debug port.
    • Set the control level to 2 via the zero-bit scans.
    • Execute the Store Format (STFMT) command (00011) to set the scan format register 1149.7 scan format.

    But I don't know what zero-bit scan is, or how this can be done. Any ideas?
  • I am able to verify the device id of the Igloo FPGA by using the following svf commands:
    !Begin Test Program
    ENDIR IDLE; !End IR scans in IDLE
    ENDDR IDLE; !End DR scans in IDLE
    SDR 32 TDI (0) TDO (1BA541CF); !32-bit DR scan
    !End Test Program

    And able to read the vybrid id by using these commands in JLINk Commander:
    J-Link>wjc 0xe
    Command 0xE (IDCODE) successfully written
    J-Link>wjd 0,32
    returns 0x4BA00477
    J-Link>

    I have also tested the chain with topjtag (evaluation version), which works fine.

    So why doesn't work with Jlink commander?