Hi,


I do not understand your description of the issue.

You attempted to do single step, but an interrupt occurred.

But there is no breakpoints in ISR.

Is the target now halted at the first instruction of the ISR? Or does it run?

Please note that we cannot provide support for issues caused by eclipse, since it is not a SEGGER product.


Best regards,
Niklas

Hi,

thanks for the clarification.

However, if I do not misinterpret your description, there is no issue in my opinion:
You attempted to do a single step, which executes the next instruction and then halts the target again.
In case an interrupt occurs, the target will be halted at the first instruction of the ISR, since this is the next instruction which is about to be executed.

Please do not hesitate to correct me if I misunderstood your issue.

Anyway, could you provide us with a J-Link Logfile?
Log output can be enabled like as follows:

• Open a connection to J-Link, e.g start J-Link Commander
• In J-Link Control Panel: (Click the J-Link symbol located in the notification / tray area in order to open J-Link Control panel)
• Open the tab "Settings"
• Next to the field "Log file" check "Override" and click "..." in order to choose a log file path.

This is also described in UM8001 Chapter 5 "Working with J-Link and J-Trace", Section 5.7 "J-Link control panel" .


Best regards,
Niklas

I am having a similar problem using an STM32F745 and the ST-Link probe with Atollic TrueStudio.


Having "googled" for similar issues, I found this on the KEIL site;
ARM: Single stepping Cortex-M7 enters pending exception handler
http://www.keil.com/support/docs/3778.htm


This describes a problem with the Cortex-M7 core which doesn’t occur with M3/M4 devices.
It is caused by the use of the DHCSR->C_MASKINTS bit which doesn’t mask pending interrupts correctly.
It suggests that the problem may be fixed in core revision r0p2 or newer.


As far as I know, my STM32F745 uses the r0p1 core.


I couldn't find any reference to this issue in the ARM Cortex-M7 Errata documents however.

Hi Forum,


a workaround for this hardware design issue of Cortex-M7 r0p0 and r0p1 devices is included since V6.10b of the J-Link software & documentation pack.

Best regards,
Niklas