We are developing an IC using a "standard" ARM cortex M0. I am trying to simulate the digital design and also emulate the same design in an FPGA. To test the M0 debug ability I have tried to use Keil, the Segger standalone tools, etc but without a successful connection.

According to our designers, this ARM core requires the standard line reset (50+ clocks with SWDIO high) but also requires one or two more clocks with SWDIO low prior to reading the device ID (or anything else). I have tried the Segger tools with various M0 device variants and they all appear to just do the 50 clocks with SWDIO high and then either try the JTAG-to-SWD switch pattern or reading the ID without the extra 1 or 2 clocks with SWDIO low first.

Is it possible to manually control the insertion of the extra SWDIO low cycles? Is there a specific device setting I can try that has this?

The ARM serial debug documentation also eludes to this line reset requirement in section 4.4 of the "ARM Debug Interface Architecture Specification ADIv5.0 to ADIv5.2":


4.4.3 Connection and line reset sequence
A debugger must use a line reset sequence to ensure that hot-plugging the serial connection does not result in
unintentional transfers. The line reset sequence ensures that the SW-DP is synchronized correctly to the header that
signals a connection.
The SWD interface does not include a reset signal. A line reset is achieved by holding the data signal HIGH for at
least 50 clock cycles, followed by at least two idle cycles. Figure 4-8 shows the interface timing for a line reset
followed by a DP DPIDR register read.


Any help would be greatly appreciated.

Thanks,
Kevin

Thanks Niklas,

I'm hoping I don't need to go down that path. Other people here in the company are using Keil with Jlink without issues but I haven't tracked down any difference with their setup and mine. I was hoping it was just a simple settings option somewhere or different device I need to use.

Hi Niklas,

The other people are using same version of Keil and Segger J-link emulator. They are using the same M0 ARM core we are trying to implement in FPGA and ASIC. They have used these tools with their ASICs but I'm not sure if they tested with an FPGA. I have captured the SWD protocol stream for the line reset and ID reads inside at the pins of the FPGA. I then used this same pattern in my Verilog simulation of the M0 core and the same result (M0 doesn't reset properly and I can't read the ID).

I think I just need 1 idle cycle after the line reset and it would work. I have verified that inserting 1 idle cycle works in RTL simulation.

Thanks,
Kevin