JMem is halted CPU for access

This site uses cookies. By continuing to browse this site, you are agreeing to our Cookie Policy.

  • JMem is halted CPU for access

    Hello.
    I use driver version 4.76a for Windows, J-Link ULTRA+ and RM48L952 chip.

    According to chapter 3.5 of UM08001_JLinkARM.pdf JMem can do access for read and write of target memory without halting CPU, but it is not so.
    My "flashing LED" program is halting when JMem is running.
    What am I doing wrong?

    Regards,
    Vitaliy.
  • Hi Vitaliy,

    You are doing nothing wrong.
    As I already explained in your other thread, this feature is not available for Cortex-A/R.
    Is support for Code Composer Studio available here?

    It may be in the future, but this requires major changes in the DLL because you need to define a memory map for such cases which defines what regions are cachable and which are not.
    For cacheable regions, memory can not be read/written during execution.
    There is no specific timeframe yet if or when this feature will be available.


    Best regards
    Alex
  • Thank you for answer.
    As I suppose, you don't want to determine cache size (or cache present) from device name or JTAG ID and turn on or off some features. Isn't it?

    And what about Cortex-M4 core with data cache (Freescale Vybrid)?

    Regards, Vitaliy.

    The post was edited 1 time, last by VVB ().

  • Hi Vitaly,

    As I suppose, you don't want to determine cache size (or cache present) from device name or JTAG ID and turn on or off some features. Isn't it?

    Forget about the JTAG ID, this does not give any useful information about device specifics...
    Making it device name dependent is on the ToDo list but I can not give you a schedule right now.

    And what about Cortex-M4 core with data cache (Freescale Vybrid)?

    For the Vybrid, there might be (not verified so far) similar problems of memory inconsistencies.
    It is a generic weakness in the concept from ARM provided to access memory while the CPU is running.


    Best regards
    Alex
  • What About for Atmel AT91SAM9XE512 (ARM926EJ-S)?

    I was trying to do the same thing, run J-Mem as a separate Windows application while the IAR debugger is running code on the target through the J-Link, or while the code is running on the target and the J-Link is connected. Running J-Mem causes the IAR debugger to do a "break" it appears, and it causes the stand-alone processor to halt. Is it possible for J-Mem to work in either of these cases, while leaving the processor running normally?
  • Hi,

    On ARM 7/9 targets (where the AT91SAM9XE is an ARM9) memory can not be read/written while the CPU is running.
    Halting the CPU is mandatory there.
    There is some workaround by using DCC and having a special handler downloaded into the target which periodically checks the DCC registers if something is to do.
    These two DCC registers (one for read and one for write) can be accessed while the CPU is running and so allow theoretically accessing memory while the CPU is running.
    Of course it is not really real-time since your application is somewhat "blocked" while the DCC handler handles the memory request.

    This functionality is already built-in IAR EWARM via the "Live Watch" Window which allows monitoring variables during run-time.


    Best regards
    Alex