Internal OS - Interrupts Disabled Where/How-Long Characterization

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  • Internal OS - Interrupts Disabled Where/How-Long Characterization

    I am using embOS on a ARM cortex-M0 processor. Is there a document that characterizes in what OS functions and for how long (# instructions), interrupts are disabled? I realize it would depend on optimizations and some would be not fixed (OS_PeekMail). But a general characterization with perhaps a range would be greatly beneficial. I can then concentrate on what API functions I need to be weary of.

    On a processor like the M0, there is no such thing as high priority interrupts. I have a known "realtime" requirement for an external interrupt that has to be met.

    Thanks,
    Todd