Internal OS - Interrupts Disabled Where/How-Long Characterization

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  • Internal OS - Interrupts Disabled Where/How-Long Characterization

    I am using embOS on a ARM cortex-M0 processor. Is there a document that characterizes in what OS functions and for how long (# instructions), interrupts are disabled? I realize it would depend on optimizations and some would be not fixed (OS_PeekMail). But a general characterization with perhaps a range would be greatly beneficial. I can then concentrate on what API functions I need to be weary of.

    On a processor like the M0, there is no such thing as high priority interrupts. I have a known "realtime" requirement for an external interrupt that has to be met.

    Thanks,
    Todd

  • Hello Todd,

    unfortunately we don't have such a document, but we measure the maximum interrupt latency caused by disabling interrupts internally.
    Please contact me via our support email address and I will send you the values.

    Best regards,
    Til
    Please read the forum rules before posting.

    Keep in mind, this is *not* a support forum.
    Our engineers will try to answer your questions between their projects if possible but this can be delayed by longer periods of time.
    Should you be entitled to support you can contact us via our support system: segger.com/ticket/
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  • Thanks Til, will do.

    I meant to include the detail that I am uisng Keil 4.70.

    Also, I would appreciate if anyone has a recommendation for any static profiling tool that would compute this kind of information.

    Todd