[SOLVED]AM335x support?

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  • [SOLVED]AM335x support?

    Hi Sir,

    I have a EVK board named BeagleBone. The cpu is AM3359. I want to debug it by using my J-Link ultra.
    I can't find any JTAG information in the reference manual of AM335x.
    Could you confirm whether J-Link ultra supports AM335x?
    Thanks a lot.


    Ohnail
    9th Feb. 2012
  • Hi Ohnail,

    We are currently working on the AM335x support.
    It is a bit tricky since
    a) There is an ICEPick device which needs to be initialized before the core is available
    b) Some coresight information in the device does not seem to be correct and needs to be setup manually.

    We will post it here as soon as AM335x support is available.


    Best regards
    Alex
  • Hi Alex,

    Thanks a lot!

    I tried to modify the script of AM3517 by myself.
    I knew the icepick id of AM3359 is 0x0B94402F and icepick code is 0x1015B3D6. And the arm core is the 12th TAP.
    But it looks J-Link can't identify all of the DPs.

    I paste the config file of BDI3000. It looks so easy.

    Source Code

    1. [INIT]
    2. [TARGET]
    3. CPUTYPE CORTEX-A8 0xCB141000
    4. CLOCK 1 ;JTAG clock
    5. POWERUP 2000 ;power-up delay
    6. TRST PUSHPULL ;TRST driver type (OPENDRAIN | PUSHPULL)
    7. ;RESET NONE ;Reset signal is not routed to the debug
    8. STARTUP RESET ;let boot code setup the system
    9. ENDIAN LITTLE ;memory model (LITTLE | BIG)
    10. WAKEUP 100
    11. MEMACCESS CORE 1 ;memory access via core (8 TCK's access delay)
    12. ;MEMACCESS AHB 1 ;memory access via AHB (8 TCK's access delay)
    13. STEPMODE OVER ;OVER or INTO
    14. VECTOR CATCH
    15. BREAKMODE HARD
    16. ; Configure ICEPick module to make Cortex-A8 DAP-TAP visible
    17. ; Polar family has A8 core on TAP28 which is in Debug TAP linking block 1
    18. SCANINIT t1:w1000:t0:w1000: ;toggle TRST,
    19. SCANINIT ch10:w1000: ;clock TCK with TMS high and wait
    20. SCANINIT i6=07:d8=89:i6=02: ;connect and select router
    21. SCANINIT d32=81000080: ;IP control: KeepPowered
    22. SCANINIT d32=ac002048: ;TAP12: DebugConnect, ForcePower, ForceActive
    23. SCANINIT d32=e0002048: ;Core#0: DebugConnect, ForcePower, ForceActive
    24. SCANINIT d32=81000081: ;IP control: KeepPowered, SysReset
    25. SCANINIT d32=ac002148: ;enable TAP12
    26. SCANINIT cl10:i10=ffff ;clock 10 times in RTI, scan bypass
    27. SCANPRED 1 6 ;count for ICEPick TAP
    28. SCANSUCC 0 0 ;no device after Cortex-A8
    29. [HOST]
    30. IP 10.10.10.30
    31. FILE dump.bin
    32. FORMAT BIN 0x80000000
    33. LOAD MANUAL
    34. PROMPT AM335x-EVM>
    35. [FLASH]
    36. [REGS]
    37. FILE regOMAP3500.def
    Display All

    The post was edited 1 time, last by ohnail ().

  • My script file

    C Source Code

    1. /*********************************************************************
    2. * SEGGER MICROCONTROLLER GmbH & Co KG *
    3. * Solutions for real time microcontroller applications *
    4. **********************************************************************
    5. * *
    6. * (c) 2011 SEGGER Microcontroller GmbH & Co KG *
    7. * *
    8. * www.segger.com Support: support@segger.com *
    9. * *
    10. **********************************************************************
    11. ----------------------------------------------------------------------
    12. Purpose : J-Link script file for TI AM3359 device.
    13. By default, only the TI ICEPick is in the JTAG chain
    14. which means that we have to add the Cortex-A8 by configuring the ICEPick.
    15. Moreover, the AM3359 also requires to set the DEBGEN signal in order to allow debugging.
    16. ---------------------------END-OF-HEADER------------------------------
    17. */
    18. /*********************************************************************
    19. *
    20. * _StoreSelDP
    21. */
    22. void _StoreSelDP(void) {
    23. JTAG_StoreIR(0xA); // DPACC command
    24. JTAG_StoreClocks(1);
    25. }
    26. /*********************************************************************
    27. *
    28. * _StoreSelAP
    29. */
    30. void _StoreSelAP(void) {
    31. JTAG_StoreIR(0xB); // APACC command
    32. JTAG_StoreClocks(1);
    33. }
    34. /*********************************************************************
    35. *
    36. * _StoreTriggerReadAPDPReg
    37. *
    38. * Function description
    39. * Triggers a read of an AP or DP register. Depends on the previous command (DPACC / APACC)
    40. */
    41. int _StoreTriggerReadAPDPReg(unsigned int RegIndex) {
    42. __int64 v; // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
    43. int BitPosData;
    44. //
    45. // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
    46. //
    47. v = 0;
    48. v |= 1; // 1 indicates read access
    49. v |= (RegIndex << 1);
    50. BitPosData = JTAG_StoreDR(v, 35);
    51. JTAG_StoreClocks(8);
    52. return BitPosData;
    53. }
    54. /*********************************************************************
    55. *
    56. * _StoreWriteAPDPReg
    57. *
    58. * Function description
    59. * Writes an AP or DP register. Depends on the previous command (DPACC / APACC)
    60. */
    61. int _StoreWriteAPDPReg(unsigned int RegIndex, __int64 Data) {
    62. __int64 v; // We need 35 bits: 32 data, 2 bit addr, 1 bit RnW
    63. int BitPosData;
    64. //
    65. // Write 35 bits (32 bits data, 2 bits addr, 1 bit RnW)
    66. //
    67. v = 0; // 0 indicates write access
    68. v |= (RegIndex << 1);
    69. v |= (Data << 3);
    70. BitPosData = JTAG_StoreDR(v, 35);
    71. JTAG_StoreClocks(8);
    72. return BitPosData;
    73. }
    74. /*********************************************************************
    75. *
    76. * _InitIcePick
    77. *
    78. * Function description
    79. * Configures the ICEPick so that the CPU core also becomes
    80. * visible in the JTAG chain.
    81. */
    82. void _InitIcePick(void) {
    83. unsigned int aDevice[2];
    84. int BitPos;
    85. int v;
    86. int ICEPickCode;
    87. int ICEPickIdCode;
    88. int DPIdCode;
    89. int i;
    90. int Speed;
    91. Report("J-Link script: Init ICEPick begin!");
    92. JTAG_Reset(); // Perform TAP reset and J-Link JTAG auto-detection
    93. if (JTAG_TotalIRLen != 6) {
    94. MessageBox1("Can not find ICE-Pick (IRLen mismatch), JTAG_TotalIRLen = ", JTAG_TotalIRLen);
    95. }
    96. JTAG_DRPre = 0;
    97. JTAG_DRPost = 0;
    98. JTAG_IRPre = 0;
    99. JTAG_IRPost = 0;
    100. JTAG_IRLen = 6;
    101. Speed = JTAG_Speed;
    102. JTAG_Speed = 50;
    103. //
    104. // Check IDCODE of ICEPick (do not confuse with ICEPICKCODE or IDCODE of JTAG-DP)
    105. //
    106. JTAG_WriteIR(4); // IDCODE instruction for ICEPick device
    107. BitPos = JTAG_WriteDR(0x00000000, 32);
    108. ICEPickIdCode = JTAG_GetU32(BitPos); // 0x0B94402F
    109. if ((ICEPickIdCode & 0x0FFFFFFF) != 0x0B94402F) { // highest nibble holds version information, so it can not be used for verification.
    110. MessageBox1("Can not find ICE-Pick (IDCODE mismatch). Expected 0x0B94402F, found: ", ICEPickIdCode);
    111. return 1;
    112. }
    113. //
    114. // Read ICEPICKCODE
    115. //
    116. JTAG_WriteIR(5);
    117. BitPos = JTAG_WriteDR(0x00000000, 32);
    118. ICEPickCode = JTAG_GetU32(BitPos); // 0x1015B3D6
    119. if ((ICEPickCode & 0x0000FFF0) != 0x0000B3D0) {
    120. MessageBox1("Connected module is not an ICEPick Module (ICEPICKCODE mismatch), found: ", ICEPickCode);
    121. return 1;
    122. }
    123. //
    124. // Put ARM core in JTAG chain
    125. //
    126. JTAG_WriteIR(7); // CONNECT
    127. JTAG_WriteDR(0x89, 8); // The ICEPick documentation (SPRUE64, 2.6 CONNECT instruction: Accessing the debug connect register). Bit 7 set means: Write debug connect register. We write 0x9 to the debug connect register which is the debug connect key.
    128. JTAG_WriteIR(2); // ROUTER (Accessing the mapped registers)
    129. v = 0
    130. | (1 << 31) // Write mapped register
    131. | (0x2C << 24) // SDTAP12 register
    132. | (1 << 13) // Debug connect
    133. | (1 << 8) // TAP select
    134. | (1 << 3) // Force active
    135. ;
    136. JTAG_WriteDR(v, 32); // v = 0xAC002108
    137. JTAG_WriteIR(0x3F); // Bypass
    138. JTAG_WriteClocks(10);
    139. //
    140. // Configure JTAG chain, so J-Link knows to which devices it has to "talk" to.
    141. // CPU core is in scan chain now, so we have to re-configure the JTAG chain settings.
    142. // The CPU core is device 0 (closest to TDO).
    143. //
    144. JTAG_IRPre=0;
    145. JTAG_DRPre=0;
    146. JTAG_IRPost=6;
    147. JTAG_DRPost=1;
    148. JTAG_IRLen=4;
    149. CPU=CORTEX_A8;
    150. JTAG_AllowTAPReset=0;
    151. //
    152. // Check core ID
    153. //
    154. JTAG_StoreIR(0xE); // Read JTAG-DP IDCODE register
    155. v = 0;
    156. BitPos = JTAG_StoreDR(v, 32); // Get ID = 0x12?
    157. DPIdCode = JTAG_GetU32(BitPos); // 0x3BA00477
    158. if (((DPIdCode & 0x00000FFF) != 0x0000002F) && ((DPIdCode & 0x00000FFF) != 0x00000477)) {
    159. MessageBox1("Can not find Cortex-A8 (IDCODE mismatch), found: ", DPIdCode);
    160. return 1;
    161. }
    162. //
    163. // Check JTAG-DP IDCODE
    164. //
    165. JTAG_StoreIR(0xE); // Read JTAG-DP IDCODE register
    166. BitPos = JTAG_StoreDR(0x00000000, 32); // Get ID
    167. v = JTAG_GetU32(BitPos);
    168. if ((v & 0xFFF) != 0x00000477) {
    169. MessageBox("Can not find JTAG-DP (IDCODE mismatch)");
    170. }
    171. return 0;
    172. }
    Display All
  • C Source Code

    1. /*********************************************************************
    2. *
    3. * _SetBP
    4. */
    5. void _SetBP(void) {
    6. __int64 Ctrl;
    7. //
    8. // Select & setup APB-AP
    9. //
    10. _StoreSelDP();
    11. _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4)); // Select AP[1], bank 0
    12. _StoreSelAP();
    13. Ctrl = 0
    14. | (2 << 0) // AP-access size. Fixed to 2: 32-bit
    15. | (1 << 4) // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
    16. | (1 << 31) // Enable software access to the Debug APB bus.
    17. ;
    18. _StoreWriteAPDPReg(0, Ctrl);
    19. //
    20. // Step 1. Disable the breakpoint being set.
    21. //
    22. _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
    23. _StoreWriteAPDPReg(3, 0x00000000);
    24. //
    25. // Step 2. Write address to the BVR, leaving the bottom 2 bits zero.
    26. //
    27. _StoreWriteAPDPReg(1, 0x54011000 + (0x40 << 2));
    28. _StoreWriteAPDPReg(3, 0x00014000);
    29. //
    30. // Step 3. Write the mask and control register to enable the breakpoint.
    31. //
    32. _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
    33. _StoreWriteAPDPReg(3, 7 | (0xF << 5) | (0 << 20));
    34. JTAG_WriteClocks(1); // Make sure that JTAG buffers are empty and breakpoint is set
    35. }
    36. /*********************************************************************
    37. *
    38. * ResetTarget
    39. */
    40. void ResetTarget(void) {
    41. int Speed;
    42. int BitPos;
    43. int Ctrl;
    44. __int64 v;
    45. Report("J-Link script: Reset");
    46. Speed = JTAG_Speed;
    47. JTAG_Speed = 100;
    48. //
    49. // Set breakpoint to halt target as fast as possible after reset
    50. //
    51. _SetBP();
    52. //
    53. // Setup JTAG config to "talk" to the ICEPick, so we can use the JTAG API functions
    54. //
    55. JTAG_DRPre = 1;
    56. JTAG_DRPost = 0;
    57. JTAG_IRPre = 4;
    58. JTAG_IRPost = 0;
    59. JTAG_IRLen = 6;
    60. //
    61. // Perform reset via ICEPick system control register, by setting the SysReset bit
    62. //
    63. JTAG_StoreIR(2); // Cmd: ROUTER
    64. v = 0x01000000; // Read SYS_CNTL
    65. JTAG_StoreDR(v, 32); // Send read register command
    66. BitPos = JTAG_StoreDR(v, 32); // Shift out register content
    67. v = JTAG_GetU32(BitPos);
    68. v &= 0x00FFFFFF;
    69. v |= 0x81000001; // Write SYS_CNTL and set SysReset bit
    70. JTAG_StoreDR(v, 32);
    71. JTAG_WriteClocks(10); // The reset needs some time to get active
    72. //
    73. // Setup JTAG config to "talk" to the Cortex-R4 again
    74. //
    75. JTAG_DRPre = 0;
    76. JTAG_DRPost = 1;
    77. JTAG_IRPre = 0;
    78. JTAG_IRPost = 6;
    79. JTAG_IRLen = 4;
    80. //
    81. // Check if CPU is halted. If not, halt it.
    82. // Select & setup APB-AP
    83. //
    84. _StoreSelDP();
    85. _StoreWriteAPDPReg(2, (1 << 24) | (0 << 4)); // Select AP[1], bank 0
    86. _StoreSelAP();
    87. Ctrl = 0
    88. | (2 << 0) // AP-access size. Fixed to 2: 32-bit
    89. | (1 << 4) // Auto increment TAR after read/write access. Increment is NOT performed on access to banked data registers 0-3.
    90. | (1 << 31) // Enable software access to the Debug APB bus.
    91. ;
    92. _StoreWriteAPDPReg(0, Ctrl);
    93. //
    94. // Read DSCR to check if CPU is halted
    95. //
    96. _StoreWriteAPDPReg(1, 0x54011000 + (0x22 << 2));
    97. _StoreTriggerReadAPDPReg(3);
    98. _StoreSelDP();
    99. BitPos = _StoreTriggerReadAPDPReg(3);
    100. v = JTAG_GetU32(BitPos + 3);
    101. _StoreSelAP();
    102. if ((v & 1) == 0) {
    103. //
    104. // If CPU did not halt after reset, halt it
    105. //
    106. Report("J-Link script: Core did not halt after reset. Halting core...");
    107. v |= (1 << 14);
    108. _StoreWriteAPDPReg(1, 0x54011000 + (0x22 << 2)); // Enable debug halt mode by writing the DSCR
    109. _StoreWriteAPDPReg(3, v);
    110. _StoreWriteAPDPReg(1, 0x54011000 + (0x24 << 2)); // Write DRCR to halt CPU
    111. _StoreWriteAPDPReg(3, 1);
    112. JTAG_WriteClocks(1);
    113. }
    114. //
    115. // Remove breakpoint
    116. //
    117. _StoreWriteAPDPReg(1, 0x54011000 + (0x50 << 2));
    118. _StoreWriteAPDPReg(3, 0);
    119. _StoreSelDP();
    120. JTAG_WriteClocks(1);
    121. JTAG_Speed = Speed;
    122. }
    123. /*********************************************************************
    124. *
    125. * InitEMU
    126. */
    127. void InitEMU(void) {
    128. EMU_ETB_IsPresent = 0;
    129. }
    130. /*********************************************************************
    131. *
    132. * InitTarget
    133. */
    134. void InitTarget(void) {
    135. int v;
    136. Report("TI AM3359 (Cortex-A8 core) J-Link script");
    137. //
    138. // By performing a TRST reset, we make sure that only the ICEPick module is in the scan chain
    139. //
    140. JTAG_TRSTPin = 0;
    141. SYS_Sleep(50);
    142. JTAG_TRSTPin = 1;
    143. SYS_Sleep(50);
    144. JTAG_Write(0x1F, 0, 6);
    145. _InitIcePick();
    146. }
    Display All
  • SEGGER - Alex wrote:

    For clarification: This is NOT a support forum where you have a claim to get a solution in a specified time.
    This is a user forum where the main intention is to get help from other users...
    We are still working on AM335x support.
    Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
    We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

    Is there any trick or workaround we could use to get the J-Link running together with the TI eval board?
  • Hello all,

    We have built a new beta version (V4.47a) which supports the AM335x.
    For more information about some special handling required for this device, please refer to UM08001, chapter "device specifics".

    Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
    We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

    We have not announced support for the AM335x series CPUs before V4.47a. We only announced the availability of an adapter for the TI 20-CTI connector.
    I agree that the AM335x EVM was not the best example but having this as an example for a board with such a connector on it does not automatically imply having support for it ready yet.


    Best regards
    Alex
  • Debugging AM335x with CodeSourcery CodeBench and "native" J-Link support

    We are using CodeSourcery CodeBench (20012.03-69), and succeeded to debug our own board (which is very similar to the TI AM335xEVM) with the "native" J-Link support from CodeBench debug sprite.
    In order to get this setup to work, we have to use a jlink settings file for the DLL, which we can specify in the debug settings. Within that file, we then force the DLL to use the AM3359 device.
    Additionally, we added the board initialization code (clocks, memroy etc.) to the board.xml file from CodeBench.

    So far, so good, starting a debug session and downloading code to external RAM works, but unfortunately the download speed is very poor, since the J-LINK DLL (V4.52c) always selects 1000KHz JTAG speed.

    1) Is there any way in the DLL settings file to force a faster JTAG speed, or any other options to speed up JTAG?

    2) We already tried to use a JLINK sript (specified in the DLL settings file), but that didn't work at all (modifying "InitTarget" and "ResetTarget" seems to destroy the recognition of the AM3359). Is it possible to get a suitable JLinkScript for the AM3359?

    3) Is it a good idea to use the board.xml for the board setup, or would it be better to use an equivalent JLinkScript (which we do not have so far, see 2)?

    Any help is very appreciated.
  • SEGGER - Alex wrote:

    Hello all,

    We have built a new beta version (V4.47a) which supports the AM335x.
    For more information about some special handling required for this device, please refer to UM08001, chapter "device specifics".

    Sorry, but it is really unsatisfying that there's still no support for the am335x devices, and no news since more than a month.
    We recently purchased the J-Link Ultra, together with your "J-Link TI-20-CTI Adapter". Since you offer this combination especially for the am335x evaluation board from TI on your web site, it should be ok to claim for support, or at least to ask for workarounds, otherwise other customers could also run into that pitfall.

    We have not announced support for the AM335x series CPUs before V4.47a. We only announced the availability of an adapter for the TI 20-CTI connector.
    I agree that the AM335x EVM was not the best example but having this as an example for a board with such a connector on it does not automatically imply having support for it ready yet.


    Best regards
    Alex
    I don't see this AM335x when I open JFlashARM, and I am using version 4.54a.
    When I chose option "Device" in "Project settings" window, I can see for TI processors AM3505 and AM3517, but not AM335x.
    So, is it possible (and how) to download firmware using Segget J-Link Pro to AM3352?
  • Hello,

    Where(!) do you want to download the firmware to?
    The AM3352 does not provide internal flash, so do you want to program external CFI NOR flash or NAND flash?
    In case of NAND flash: This requires a so-called custom RAMCode since there is no generic way of supporting NAND flash since the user is free to connect it to an available NAND flash controller or to almost any GPIO pins on the device.


    Best regards
    Alex
  • SEGGER - Alex wrote:

    Hello,

    Where(!) do you want to download the firmware to?
    The AM3352 does not provide internal flash, so do you want to program external CFI NOR flash or NAND flash?
    In case of NAND flash: This requires a so-called custom RAMCode since there is no generic way of supporting NAND flash since the user is free to connect it to an available NAND flash controller or to almost any GPIO pins on the device.


    Best regards
    Alex
    Hello,

    We have custom RamCode for flashing NAND.
    Problem is that I we don't see the Segger project setup for am335x!
    How can load RamCode to RAM?!

    Best regards,
    Strahinja